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DS125DF1610: DS125DF1610 Channel lost lock

Part Number: DS125DF1610

Hello,

My customer has been using DS125DF1610 and they found the one channel lost lock during first round debugging. The related channel register is set as the following.

//init step
//reset retimer

 

//select retimer1 shared reg 
0xff, 0x00

//25m ref clock
0x02,0x00

//select retimer1 channel reg
0xff, 0x01

//select retimer1 channel 10
0xfd, 0x04
0xfc, 0x00

//cdr reset
0xa, 0x1c

//Adapt Mode Configuration
0x31, 0x60

//enable dfe
0x1e, 0xe1

//date rate select
0x2f, 0xb6
//no cross point

//CTLE Bandwidth Select
0x8d, 0x00

//Edge rate control  and VGA Configuration
0x8e, 0x02

//enable cdr lock and signal interrupt
0x79, 0x13

--cdr reset release
0xa 0x00

 

1、Could anyone help check the register setting and suggest if there is anything wrong?

2、0x2f,reigister is 0xb6,  retimer register 0x34 shows ppm err, why this happens?is it related to data rate or clocking?

3. Could we provide a reference setting for this device?


  • Hi, my inputs below.

    1. Could anyone help check the register setting and suggest if there is anything wrong?
      • I don't see anything here that would explain a CDR lock issue.
      • Question: how did customer determin that adapt mode 2 is ideal here
      • Question: What is the approximate insertion loss at 5GHz for the retimer input channel
      • Question: Can the customner provide HEO and VEO readings (i.e. channel registers 0x27 and 0x28) for the channel in quetstion
    2. 0x2f,reigister is 0xb6,  retimer register 0x34 shows ppm err, why this happens?is it related to data rate or clocking
      1. No, this is a normal reading. The PPM_error_ready set to 1 means that a ppm_counter check cycle was completed and not necesarily that a ppm error  was observed
    3. Could we provide a reference setting for this device?
      • To be able to provide a reference setting i would need more info on the application, such as basic block diagram and approximate insertion loss for both the rertimer input and output channels

    Thanks,

    Rodrigo Natal

    HSSC Applications Engineer



  • Correction on my previous message: customer is using adapt mode 3 not adapt mode 2

  • 1.Could anyone help check the register setting and suggest if there is anything wrong?

           I don't see anything here that would explain a CDR lock issue.

    • Question: how did customer determin that adapt mode 2 is ideal here

                  reply      :   We are using adapt mode 3 not adapt mode 2

    • Question: What is the approximate insertion loss at 5GHz for the retimer input channel

    reply     :   We are using 10G(XFI).

                      Optical Module(sfp+ rx): 10GRX-->(2235.32 mil)-->Coupling capacitor-->(1725.33 mil)--> (CH10 C RX)DS125DF160 ->(CH10 C TX)-->(939.21 mil)-->CN7890(Multi-Core CPU)

     

                      Optical Module(sfp+ tx): 10GTX-->(2158.23 mil)<--Coupling capacitor<--(2696.41 mil<--(CH10 C TX)<--DS125DF160(CH10 C RX)<--(2952.65 mil)<--CN7890(Multi-Core CPU)

     

    • Question: Can the customner provide HEO and VEO readings (i.e. channel registers 0x27 and 0x28) for the channel in quetstion

                 reply        : REG[0x27] = 0x00
                                    REG[0x28] = 0x00

    3.Could we provide a reference setting for this device?

           To be able to provide a reference setting i would need more info on the application, such as basic block diagram and approximate insertion loss for both the rertimer input and output channels

            reply  :

                      Optical Module(SFP+ Rx): 10GRX-->(2235.32mil)-->Coupling capacitor-->(1725.33mil)--> (CH10 C RX)DS125DF160 ->(CH10 C TX)-->(939.21mil)-->CN7890(Multi-Core CPU)

     

                      Optical Module(SFP+ Tx): 10GTX-->(2158.23mil)<--Coupling capacitor<--(2696.41mil<--(CH10 C TX)<--DS125DF160(CH10 C RX)<--(2952.65mil)<--CN7890(Multi-Core CPU)

                     

                     

                     

    4.the lastest reg value readed back from device(RX Retimer):

       question:

        Initialization Setup:

           --cdr reset(reg[0x0a]=0x5c)

           --Adapt Mode Configuration(reg[0x31]=0x63)

           --Data rate selection(reg[0x2F]=0xB6)

           --cdr reset release(reg[0x0a]=0x50)

        But the value read from the device registers 0x2f is 0x36. The reg[0x2f] value of the read from the device is different from the set value. Why?

    shared               

    reg[00H]:0000H
    reg[01H]:0071H
    reg[02H]:0000H
    reg[03H]:0000H
    reg[04H]:0001H
    reg[05H]:0008H
    reg[06H]:0000H
    reg[07H]:0005H
    reg[08H]:0000H
    reg[09H]:0004H
    reg[0AH]:0001H
    reg[0BH]:0050H
    reg[0CH]:0000H
    reg[0DH]:0003H
    reg[0EH]:0000H
    reg[0FH]:00FFH
    reg[10H]:00FFH
    reg[11H]:0000H

    channel 10 (5A)

    reg[00H]:0000H
    reg[01H]:0081H
    reg[02H]:0004H
    reg[03H]:0000H
    reg[04H]:0001H
    reg[05H]:0001H
    reg[06H]:0001H
    reg[07H]:0001H
    reg[08H]:0060H
    reg[09H]:0000H
    reg[0AH]:0050H
    reg[0BH]:006FH
    reg[0CH]:0008H
    reg[0DH]:00B4H
    reg[0EH]:0093H
    reg[0FH]:0069H

    reg[10H]:003AH
    reg[11H]:0020H
    reg[12H]:00E0H
    reg[13H]:0090H
    reg[14H]:0000H
    reg[15H]:0012H
    reg[16H]:007AH
    reg[17H]:0036H
    reg[18H]:0040H
    reg[19H]:0020H
    reg[1AH]:00A0H
    reg[1BH]:0003H
    reg[1CH]:0090H
    reg[1DH]:0000H
    reg[1EH]:00E1H
    reg[1FH]:0055H

    reg[20H]:0000H
    reg[21H]:0000H
    reg[22H]:0000H
    reg[23H]:0040H
    reg[24H]:0040H
    reg[25H]:0000H
    reg[26H]:0000H
    reg[27H]:0000H
    reg[28H]:0000H
    reg[29H]:0000H
    reg[2AH]:0030H
    reg[2BH]:000FH
    reg[2CH]:00F2H
    reg[2DH]:0004H
    reg[2EH]:0000H
    reg[2FH]:0036H   //why?

    reg[30H]:0000H
    reg[31H]:0063H
    reg[32H]:0011H
    reg[33H]:0088H
    reg[34H]:00BFH
    reg[35H]:001FH
    reg[36H]:0030H
    reg[37H]:0017H
    reg[38H]:0000H
    reg[39H]:0000H
    reg[3AH]:0000H
    reg[3BH]:003CH
    reg[3CH]:0093H
    reg[3DH]:0035H
    reg[3EH]:0043H
    reg[3FH]:00C7H

    reg[40H]:0000H
    reg[41H]:0001H
    reg[42H]:0004H
    reg[43H]:0010H
    reg[44H]:0040H
    reg[45H]:0008H
    reg[46H]:0002H
    reg[47H]:0080H
    reg[48H]:0003H
    reg[49H]:000CH
    reg[4AH]:0030H
    reg[4BH]:0041H
    reg[4CH]:0050H
    reg[4DH]:00C0H
    reg[4EH]:0060H
    reg[4FH]:0090H

    reg[50H]:0088H
    reg[51H]:0082H
    reg[52H]:00A0H
    reg[53H]:0046H
    reg[54H]:0052H
    reg[55H]:008CH
    reg[56H]:00B0H
    reg[57H]:00C8H
    reg[58H]:0057H
    reg[59H]:005DH
    reg[5AH]:0069H
    reg[5BH]:0075H
    reg[5CH]:00D5H
    reg[5DH]:0099H
    reg[5EH]:0096H
    reg[5FH]:00A5H

    reg[60H]:0000H
    reg[61H]:0000H
    reg[62H]:0000H
    reg[63H]:0000H
    reg[64H]:0000H
    reg[65H]:0000H
    reg[66H]:0000H
    reg[67H]:0020H
    reg[68H]:0000H
    reg[69H]:000AH
    reg[6AH]:0022H
    reg[6BH]:0040H
    reg[6CH]:0000H
    reg[6DH]:0000H
    reg[6EH]:0000H
    reg[6FH]:0000H

    reg[70H]:0003H
    reg[71H]:0020H
    reg[72H]:0000H
    reg[73H]:0000H
    reg[74H]:0000H
    reg[75H]:0000H
    reg[76H]:0022H
    reg[77H]:001AH
    reg[78H]:0024H
    reg[79H]:0013H
    reg[7AH]:0000H
    reg[7BH]:0000H
    reg[7CH]:0000H
    reg[7DH]:0048H
    reg[7EH]:0013H
    reg[7FH]:003AH

    reg[80H]:0000H
    reg[81H]:00E4H
    reg[82H]:0000H
    reg[83H]:0000H
    reg[84H]:0000H
    reg[85H]:0000H
    reg[86H]:0000H
    reg[87H]:0000H
    reg[88H]:0000H
    reg[89H]:000BH
    reg[8AH]:00E4H
    reg[8BH]:0000H
    reg[8CH]:0000H
    reg[8DH]:0000H
    reg[8EH]:001CH
    reg[8FH]:000CH

    reg[90H]:0000H
    reg[91H]:0000H
    reg[92H]:0000H
    reg[93H]:0000H
    reg[94H]:0000H
    reg[95H]:0000H
    reg[96H]:001EH
    reg[97H]:0000H
    reg[98H]:000CH
    reg[99H]:003FH
    reg[9AH]:003FH
    reg[9BH]:0002H

     

     

  • Thank you for providing the details regarding the application. Below to recap are the high-speed ingress and egress data paths:

    • Ingress Path
      • Optical Module(sfp+ rx): 10GRX-->(2235.32 mil)-->Coupling capacitor-->(1725.33 mil)--> (CH10 C RX)DS125DF160 ->(CH10 C TX)-->(939.21 mil)-->CN7890(Multi-Core CPU)
    • Egress path
      • Optical Module(sfp+ tx): 10GTX-->(2158.23 mil)<--Coupling capacitor<--(2696.41 mil<--(CH10 C TX)<--DS125DF160(CH10 C RX)<--(2952.65 mil)<--CN7890(Multi-Core CPU)

    My inputs are the following

    • The PCB channel between SFP+ module and the retimer is very short. The same is true for the channel between the CPU and the retimer. You may consider setting the retimer to adapt mode 0 and forcing CTLE value of 0 by adding the I2C channel register commands below to your configuration.


    REG

    Value

    Comment

    0x31

    0x00

    Set Adapt mode 0

    0x2D

    0x88

    Enable EQ override

    0x03

    0x00

    Set EQ = 00

    0x3A

    0x00

    Set EQ = 00

    0x0A

    0x1C

    Puts the CDR into RESET

    0x0A

    0x10

    Releases the CDR from reset

    • The SFP+ module already implements AC coupling caps on its inputs and outputs. Thus, you do not need to implenent additional external capacitors in between the SFP+ module electrical inputs and outputs and the TI retimer.
    • You mention that you are observing a content of 0x36 on register 0x2F instead of 0xB6 which is the value you believe are writing. 0x36 is the default value for this register. Thus if you are reading that value then you either did not execute the channel registe write correctly, or perhaps you implemented some type of reset operation, such as a channel registers reset via 0x00[2]

    Thanks,

    Rodrigo Natal

    HSSC Applications Engineer 

  • The CDR is still not locked. the lastest reg value readed back from device(RX Retimer)

    shared:

    reg[00H]:0000H
    reg[01H]:0071H
    reg[02H]:0000H
    reg[03H]:0000H
    reg[04H]:0001H
    reg[05H]:0008H
    reg[06H]:0000H
    reg[07H]:0005H
    reg[08H]:0000H
    reg[09H]:0004H
    reg[0AH]:0001H
    reg[0BH]:0050H
    reg[0CH]:0000H
    reg[0DH]:0082H
    reg[0EH]:0000H
    reg[0FH]:00FFH
    reg[10H]:00FFH
    reg[11H]:0000H

    channel 10
    reg[00H]:0000H
    reg[01H]:0080H
    reg[02H]:0000H
    reg[03H]:0000H
    reg[04H]:0001H
    reg[05H]:0001H
    reg[06H]:0001H
    reg[07H]:0001H
    reg[08H]:0060H
    reg[09H]:0000H
    reg[0AH]:0010H
    reg[0BH]:006FH
    reg[0CH]:0008H
    reg[0DH]:00B4H
    reg[0EH]:0093H
    reg[0FH]:0069H

    reg[10H]:003AH
    reg[11H]:0020H
    reg[12H]:00E0H
    reg[13H]:0090H
    reg[14H]:0000H
    reg[15H]:0012H
    reg[16H]:007AH
    reg[17H]:0036H
    reg[18H]:0040H
    reg[19H]:0020H
    reg[1AH]:00A0H
    reg[1BH]:0003H
    reg[1CH]:0090H
    reg[1DH]:0000H
    reg[1EH]:00E1H
    reg[1FH]:0055H

    reg[20H]:0000H
    reg[21H]:0000H
    reg[22H]:0000H
    reg[23H]:0040H
    reg[24H]:0040H
    reg[25H]:0000H
    reg[26H]:0000H
    reg[27H]:0000H
    reg[28H]:0000H
    reg[29H]:0000H
    reg[2AH]:0030H
    reg[2BH]:000FH
    reg[2CH]:00F2H
    reg[2DH]:0088H
    reg[2EH]:0000H
    reg[2FH]:00B6H


    reg[30H]:0000H
    reg[31H]:0000H
    reg[32H]:0011H
    reg[33H]:0088H
    reg[34H]:00BFH
    reg[35H]:001FH
    reg[36H]:0030H
    reg[37H]:0000H
    reg[38H]:0000H
    reg[39H]:0000H
    reg[3AH]:0000H
    reg[3BH]:0038H
    reg[3CH]:00F1H
    reg[3DH]:0035H
    reg[3EH]:0043H
    reg[3FH]:00C7H

    reg[40H]:0000H
    reg[41H]:0001H
    reg[42H]:0004H
    reg[43H]:0010H
    reg[44H]:0040H
    reg[45H]:0008H
    reg[46H]:0002H
    reg[47H]:0080H
    reg[48H]:0003H
    reg[49H]:000CH
    reg[4AH]:0030H
    reg[4BH]:0041H
    reg[4CH]:0050H
    reg[4DH]:00C0H
    reg[4EH]:0060H
    reg[4FH]:0090H

    reg[50H]:0088H
    reg[51H]:0082H
    reg[52H]:00A0H
    reg[53H]:0046H
    reg[54H]:0052H
    reg[55H]:008CH
    reg[56H]:00B0H
    reg[57H]:00C8H
    reg[58H]:0057H
    reg[59H]:005DH
    reg[5AH]:0069H
    reg[5BH]:0075H
    reg[5CH]:00D5H
    reg[5DH]:0099H
    reg[5EH]:0096H
    reg[5FH]:00A5H

    reg[60H]:0000H
    reg[61H]:0000H
    reg[62H]:0000H
    reg[63H]:0000H
    reg[64H]:0000H
    reg[65H]:0000H
    reg[66H]:0000H
    reg[67H]:0020H
    reg[68H]:0000H
    reg[69H]:000AH
    reg[6AH]:0022H
    reg[6BH]:0040H
    reg[6CH]:0000H
    reg[6DH]:0000H
    reg[6EH]:0000H
    reg[6FH]:0000H

    reg[70H]:0003H
    reg[71H]:0020H
    reg[72H]:0000H
    reg[73H]:0000H
    reg[74H]:0000H
    reg[75H]:0000H
    reg[76H]:0022H
    reg[77H]:001AH
    reg[78H]:0024H
    reg[79H]:0013H
    reg[7AH]:0000H
    reg[7BH]:0000H
    reg[7CH]:0000H
    reg[7DH]:0048H
    reg[7EH]:0013H
    reg[7FH]:003AH

    reg[80H]:0000H
    reg[81H]:00E4H
    reg[82H]:0000H
    reg[83H]:0000H
    reg[84H]:0000H
    reg[85H]:0000H
    reg[86H]:0000H
    reg[87H]:0000H
    reg[88H]:0000H
    reg[89H]:0000H
    reg[8AH]:0000H
    reg[8BH]:0000H
    reg[8CH]:0000H
    reg[8DH]:0000H
    reg[8EH]:001CH
    reg[8FH]:0000H

    reg[90H]:0000H
    reg[91H]:0000H
    reg[92H]:0000H
    reg[93H]:0000H
    reg[94H]:0000H
    reg[95H]:0000H
    reg[96H]:001EH
    reg[97H]:0000H
    reg[98H]:000CH
    reg[99H]:003FH
    reg[9AH]:003FH
    reg[9BH]:0002H

  • Hi. I'mn ot able to figure out what registers have what value from this data log. Would you be able to provide channel register values in a format similar to below i.e. using addressing scheme as per the retimer product datasheet? The values below are an example log of register values captured using TI's SigCon Architect GUI.

    0x0 Shared Registers_0x00 00

    0x1 Shared Registers_0x01 71

    0x2 Shared Registers_0x02 00

    0x3 Shared Registers_0x03 00

    0x4 Shared Registers_0x04 01

    0x5 Shared Registers_0x05 08

    0x6 Shared Registers_0x06 00

    0x7 Shared Registers_0x07 05

    0x8 Shared Registers_0x08 00

    0x9 Shared Registers_0x09 00

    0xA Shared Registers_0x0A 01

    0xB Shared Registers_0x0B 40

    0xC Shared Registers_0x0C 00

    0xD Shared Registers_0x0D 80

    0xE Shared Registers_0x0E 00

    0xF Shared Registers_0x0F FF

    0x10 Shared Registers_0x10 FF

    0x11 Shared Registers_0x11 00

    0xFC Global Registers_0xFC 00

    0xFD Global Registers_0xFD 02

    0xFE Global Registers_0xFE 03

    0xFF Global Registers_0xFF 01

    0x0 Rx/Tx 0A_0x00 00

    0x1 Rx/Tx 0A_0x01 00

    0x2 Rx/Tx 0A_0x02 00

    0x3 Rx/Tx 0A_0x03 00

    0x4 Rx/Tx 0A_0x04 01

    0x5 Rx/Tx 0A_0x05 01

    0x6 Rx/Tx 0A_0x06 01

    0x7 Rx/Tx 0A_0x07 01

    0x8 Rx/Tx 0A_0x08 60

    0x9 Rx/Tx 0A_0x09 00

    0xA Rx/Tx 0A_0x0A 50

    0xB Rx/Tx 0A_0x0B 6F

    0xC Rx/Tx 0A_0x0C 08

    0xD Rx/Tx 0A_0x0D B4

    0xE Rx/Tx 0A_0x0E 93

    0xF Rx/Tx 0A_0x0F 69

    0x10 Rx/Tx 0A_0x10 3A

    0x11 Rx/Tx 0A_0x11 20

    0x12 Rx/Tx 0A_0x12 E0

    0x13 Rx/Tx 0A_0x13 90

    0x14 Rx/Tx 0A_0x14 00

    0x15 Rx/Tx 0A_0x15 12

    0x16 Rx/Tx 0A_0x16 7A

    0x17 Rx/Tx 0A_0x17 36

    0x18 Rx/Tx 0A_0x18 40

    0x19 Rx/Tx 0A_0x19 20

    0x1A Rx/Tx 0A_0x1A A0

    0x1B Rx/Tx 0A_0x1B 03

    0x1C Rx/Tx 0A_0x1C 90

    0x1D Rx/Tx 0A_0x1D 00

    0x1E Rx/Tx 0A_0x1E E9

    0x1F Rx/Tx 0A_0x1F 55

    0x20 Rx/Tx 0A_0x20 00

    0x21 Rx/Tx 0A_0x21 00

    0x22 Rx/Tx 0A_0x22 00

    0x23 Rx/Tx 0A_0x23 40

    0x24 Rx/Tx 0A_0x24 40

    0x25 Rx/Tx 0A_0x25 90

    0x26 Rx/Tx 0A_0x26 00

    0x27 Rx/Tx 0A_0x27 00

    0x28 Rx/Tx 0A_0x28 00

    0x29 Rx/Tx 0A_0x29 01

    0x2A Rx/Tx 0A_0x2A 30

    0x2B Rx/Tx 0A_0x2B 0F

    0x2C Rx/Tx 0A_0x2C F2

    0x2D Rx/Tx 0A_0x2D 04

    0x2E Rx/Tx 0A_0x2E 00

    0x2F Rx/Tx 0A_0x2F 36

    0x30 Rx/Tx 0A_0x30 00

    0x31 Rx/Tx 0A_0x31 20

    0x32 Rx/Tx 0A_0x32 11

    0x33 Rx/Tx 0A_0x33 88

    0x34 Rx/Tx 0A_0x34 BF

    0x35 Rx/Tx 0A_0x35 1F

    0x36 Rx/Tx 0A_0x36 30

    0x37 Rx/Tx 0A_0x37 00

    0x38 Rx/Tx 0A_0x38 00

    0x39 Rx/Tx 0A_0x39 00

    0x3A Rx/Tx 0A_0x3A 00

    0x3B Rx/Tx 0A_0x3B 24

    0x3C Rx/Tx 0A_0x3C 83

    0x3D Rx/Tx 0A_0x3D 35

    0x3E Rx/Tx 0A_0x3E 43

    0x3F Rx/Tx 0A_0x3F C7

    0x40 Rx/Tx 0A_0x40 00

    0x41 Rx/Tx 0A_0x41 01

    0x42 Rx/Tx 0A_0x42 04

    0x43 Rx/Tx 0A_0x43 10

    0x44 Rx/Tx 0A_0x44 40

    0x45 Rx/Tx 0A_0x45 08

    0x46 Rx/Tx 0A_0x46 02

    0x47 Rx/Tx 0A_0x47 80

    0x48 Rx/Tx 0A_0x48 03

    0x49 Rx/Tx 0A_0x49 0C

    0x4A Rx/Tx 0A_0x4A 30

    0x4B Rx/Tx 0A_0x4B 41

    0x4C Rx/Tx 0A_0x4C 50

    0x4D Rx/Tx 0A_0x4D C0

    0x4E Rx/Tx 0A_0x4E 60

    0x4F Rx/Tx 0A_0x4F 90

    0x50 Rx/Tx 0A_0x50 88

    0x51 Rx/Tx 0A_0x51 82

    0x52 Rx/Tx 0A_0x52 A0

    0x53 Rx/Tx 0A_0x53 46

    0x54 Rx/Tx 0A_0x54 52

    0x55 Rx/Tx 0A_0x55 8C

    0x56 Rx/Tx 0A_0x56 B0

    0x57 Rx/Tx 0A_0x57 C8

    0x58 Rx/Tx 0A_0x58 57

    0x59 Rx/Tx 0A_0x59 5D

    0x5A Rx/Tx 0A_0x5A 69

    0x5B Rx/Tx 0A_0x5B 75

    0x5C Rx/Tx 0A_0x5C D5

    0x5D Rx/Tx 0A_0x5D 99

    0x5E Rx/Tx 0A_0x5E 96

    0x5F Rx/Tx 0A_0x5F A5

    0x60 Rx/Tx 0A_0x60 00

    0x61 Rx/Tx 0A_0x61 00

    0x62 Rx/Tx 0A_0x62 00

    0x63 Rx/Tx 0A_0x63 00

    0x64 Rx/Tx 0A_0x64 00

    0x65 Rx/Tx 0A_0x65 00

    0x66 Rx/Tx 0A_0x66 00

    0x67 Rx/Tx 0A_0x67 20

    0x68 Rx/Tx 0A_0x68 00

    0x69 Rx/Tx 0A_0x69 0A

    0x6A Rx/Tx 0A_0x6A 22

    0x6B Rx/Tx 0A_0x6B 40

    0x6C Rx/Tx 0A_0x6C 00

    0x6D Rx/Tx 0A_0x6D 00

    0x6E Rx/Tx 0A_0x6E 00

    0x6F Rx/Tx 0A_0x6F 00

    0x70 Rx/Tx 0A_0x70 03

    0x71 Rx/Tx 0A_0x71 20

    0x72 Rx/Tx 0A_0x72 00

    0x73 Rx/Tx 0A_0x73 00

    0x74 Rx/Tx 0A_0x74 00

    0x75 Rx/Tx 0A_0x75 00

    0x76 Rx/Tx 0A_0x76 22

    0x77 Rx/Tx 0A_0x77 1A

    0x78 Rx/Tx 0A_0x78 00

    0x79 Rx/Tx 0A_0x79 10

    0x7A Rx/Tx 0A_0x7A 00

    0x7B Rx/Tx 0A_0x7B 00

    0x7C Rx/Tx 0A_0x7C 00

    0x7D Rx/Tx 0A_0x7D 48

    0x7E Rx/Tx 0A_0x7E 13

    0x7F Rx/Tx 0A_0x7F 3A

    0x80 Rx/Tx 0A_0x80 00

    0x81 Rx/Tx 0A_0x81 E4

    0x82 Rx/Tx 0A_0x82 00

    0x83 Rx/Tx 0A_0x83 00

    0x84 Rx/Tx 0A_0x84 00

    0x85 Rx/Tx 0A_0x85 00

    0x86 Rx/Tx 0A_0x86 4C

    0x87 Rx/Tx 0A_0x87 00

    0x88 Rx/Tx 0A_0x88 00

    0x89 Rx/Tx 0A_0x89 00

    0x8A Rx/Tx 0A_0x8A 00

    0x8B Rx/Tx 0A_0x8B 00

    0x8C Rx/Tx 0A_0x8C 00

    0x8D Rx/Tx 0A_0x8D 02

    0x8E Rx/Tx 0A_0x8E 1C

    0x8F Rx/Tx 0A_0x8F 00

    0x90 Rx/Tx 0A_0x90 00

    0x91 Rx/Tx 0A_0x91 00

    0x92 Rx/Tx 0A_0x92 00

    0x93 Rx/Tx 0A_0x93 00

    0x94 Rx/Tx 0A_0x94 00

    0x95 Rx/Tx 0A_0x95 00

    0x96 Rx/Tx 0A_0x96 04

    0x97 Rx/Tx 0A_0x97 00

    0x98 Rx/Tx 0A_0x98 0C

    0x99 Rx/Tx 0A_0x99 3F

    0x9A Rx/Tx 0A_0x9A 3F

    0x9B Rx/Tx 0A_0x9B 00