This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

DS90UB954-Q1: Register setting

Part Number: DS90UB954-Q1

Hi team,

I'm considering to use 953 and 954 system.

I have some questions for register setting and usage of setting.

<DS90UB954>

・0x4C FPD3_PORT_SEL Register

Is the "RX port x registers" in this register and the "FPD3 RX Port x Reserved Registers" of the 0xB0 IND_ACC_CTL Register the same?

・0xD5 AEQ_MIN_MAX Register

Is there a calculation formula to show the setting of AEQ and its effect?

I do not know what kind of setting should be done.

Which register is it shown reg_35 [5: 4] described in ADAPTIVE_EQ_FLOOR_VALUE's description?

<DS90UB953>

・0x01 RESET_CTL_Register

What is the difference DIGITAL_RESET_1 and 0?

・0xB0 IND_ACC_CTL

I did not find the description about 001: FPD 3 TX Registers in IA_SEL, but what can be set up when 001 is written to IA_SEL?

I am troubled with setting registers.

Please tell me about the registers above.

Best regards,

Tomoaki Yoshida

  • Hello,

    No 0x4C is not same as indirect access registers 0xB0, B1, B2. The indirect access is primarily used for setting up test modes such as the pattern generator and enabling the CMLout and typically not used for normal operation.

    ADAPTIVE_EQ_FLOOR_VALUE in register 0xD5. Please see description in DS90UB954-Q1 datasheet section 7.4.9 for more details. The AEQ settings are should not need changing from default for most system use cases.

    DIGITAL_RESET0 does not set I2C registers back to default values so it is a way to reset the 954 by SW command without having to reprogram device modes, I2C aliasing, etc.
  • Hi Liam-san,

    Thank you for your support.

    I have some additional questions.

    #1 0xD5 AEQ_MIN_MAX Register of DS90UB954

    In the field of ADAPTIVE_EQ_FLOOR_VALUE, it is has the following description;

    "When AEQ floor is enabled by register {reg_35[5:4]} the starting EQ gain setting for AEQ adaption is given by this register."

    Which register is reg_35[5:4] wrriten above?

    I think that it means bit2 of 0xD2 is SET_AEQ_FLOOR.

    Is this right?

    #2 0xB0 IND_ACC_CTL of DS90UB953

    I did not find the description about 001: FPD 3 TX Registers in IA_SEL, but what can be set up when 001 is written to IA_SEL?

    Is this also for test mode setting?

    I would like to know what it can do by setting this up.

    Best regards,

    Tomoaki Yoshida

     

  • Yes, this is a typo and should read SET_AEQ_FLOOR instead of AEQ_FLOOR.
    These are used for test and debug, for example the IA registers are used for enabling CMLOUT in section 7.4.10.1.
  • Hi Liam-san,

    Thank you for your support.

    I have some additional questions for error status register.

    #1 (954)
    What is the difference between 0x04[2] LOCK and 0x4D[0] LOCK_STS.
    The 0x4D indicates lock status on either RX_PORT_ 0 or 1 port.
    I think 0x04 is ORing the LOCK state of RX_PORT_ 0 and 1.
    Is this right?

    #2(954)
    The port number indicated by 0x4D and 0x4E can be set by 0x4C[4], is this correct?


    I am trying to understand CSI_RX_STS register by reading the data sheet.
    Can you judge whether my understanding is correct as follows?

    #3(954)
    This register is used for error detection of FPD-Link III frame input at 954 during CSI-2 mode operation written in 954 data sheet 7.4 Device Functional Modes.
    Is this correct?


    #4
    Serializer 953 performs error check (& ECC correction) on the CSI-2 packet received from the sensor or the like, and then sets the corresponding bit of the CSI_ERR_STATUS register to 1 if Checksum / ECC / Line length error exists.
    Correct the header when ECC 1 bit error occurs.
    However, irrespective of whether or not an error is detected in the CSI-2 packet, each CSI-2 packet including ECC and Checksum is embedded in the frame of the FPD-Link III and transmitted to 954.
    Is this correct?

    #5
    954 decodes the received FPD-Link III frame, extracts the CSI-2 packet, and checks the ECC, Check sum, and CSI-2 packet length.
    If there is an error, 1 is set to the corresponding bit of CSI_RX_STS.
    Is this correct?

    #6
    From the above #3,#4 and #5, when any bit of CSI_RX_STS of 954 is 1, it is one of the following status.
    · An error detected at the time 953 received CSI-2 was detected again at 954 (except for ECC 1 bit error because it is corrected at the time of receiving at 953) or
    - Error occurred newly at 954 due to abnormality occurring during FPD-Link III transmission
    Is this correct?


    Best regards,
    Tomoaki Yoshida
  • Hi Liam-san,

    Any update on this issue?

    Please tell me on these.


    Best regards,
    Tomoaki Yoshida
  • HI Liam-san,

    I have some additional questions.

    We want to detect PLL lock of forward channel and back channel, and CRC error of forward channel and back channel.
    If these are detected, I want to interrupt and apply external output with INTB or GPIO.

    #7 954.0x51 SENSOR_STS_0
    I would like to know the detection conditions of alarm flags.
    Especially, BCC_ALARM(0x51[4]) and LINK_DETECT_ALARM(0x51[3]).
    Will LINK_DETECT become 1 if communication of 953-954 is established?

    #8
    I want to output an interrupt to INTB or GPIO by detecting an interrupt at 954 0x51.
    Please tell me if there is a way to do so.

    #9 953.0x51 GENERAL_STATUS
    What is the state when HS_PLL_LOCK(0x51[2]) is High?
    I understand that the clock of FPD-LINK III is locked against the input clock of CSI-2.
    Is this correct?

    I think that HS_PLL_LOCK of 953 and LOCK of 954 are irrelevant, so I think that the situation as shown below is possible.
    Is this correct?
    ・The LOCK of 954 is high and the HS_PLL_LOCK is low
    ・The LOCK of 954 is low and the HS_PLL_LOCK is high
    I think that we need to confirm both registers to confirm the certainty of communication.


    Best regards,
    Tomoaki Yoshida
  • Hi Liam-san,

    I would be grateful if you could let us have your answer concerning this matter.

    Best regards,
    Tomoaki Yoshida
  • Hello Yoshida-san,

    sorry for the delay. Please it would be helpful not to add questions to topics that have already been answered as this is difficult to track. Especially when questions are not related, the preference would be to start new topic question.
  • 1. From datasheet
    LOCK_STS =FPD-Link III receiver is locked to incoming data
    1: Receiver is locked to incoming data
    0: Receiver is not locked
    LOCK_STS_CHG Lock Status Changed
    This bit is set if a change in receiver lock status has been detected
    since the last read of this register. Current lock status is available in
    the LOCK_STS bit of this register This bit is cleared on read.

    2. Yes
    3. correct
    4. correct
    5. correct
    6. yes
  • Please follow datasheet registers only. If not in datasheet then it is reserved.