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  • TI Thinks Resolved

DS90UH948-Q1: Skew for RIN

Part Number: DS90UH948-Q1

Hi,

I would like you to confirm about requirement for skew of RIN0 and RIN1.

In general, we believe that RINx should be traced same length. But could you please confirm which error range should be available ?

Best Regards, 

  • Hi,

    Could you please send me your feedback ?

    Best Regards,
  • In reply to Ryuuichi machida:

    Hi,

    I really need your feedback about this.

    Could you please send me your status ?

    BR,

  • In reply to Ryuuichi machida:

    Hello Ryuuichi,

    I'm sorry for the delay.

    The DS90UH948-Q1 features de-skew functionality that allows up to 4 pixel clocks of skew between the FPD-Link III lanes. At 170 MHz (the max pixel clock frequency), that is ~23.5ns of allowable skew.

    Regards,
    Davor
  • In reply to Davor Glisic:

    Hello Davor-san,

    Thank you for your reply.

    >The DS90UH948-Q1 features de-skew functionality that allows up to 4 pixel clocks of skew between the FPD-Link III lanes.

    If you know, could you please tell me which document above sentence is described ?

    (If this information is not described in any official document, please let me know. At least I can not find this on datasheet.)

    Best Regards,

  • In reply to Ryuuichi machida:

    Hello Ryuuichi,

    At the moment, this information is not described in any official document. I will log this documentation omission so it can be included in the next datasheet revision.

    Regards,
    Davor
  • In reply to Davor Glisic:

    Hi Davor-san,

    Thank you for your reply.
    Please keep this thread to open state until you include this info to datasheet.

    Best Regards,
  • In reply to Ryuuichi machida:

    Hi Davor-san,

    Let me confirm one thing just in case.

    * Is "4 pixel clocks" correct ?
    In general, delay by board per 1 mm is in "ps" unit.
    So, if "us" unit as delay is available, this device have too much margin.
    Could you please confirm whether "unit" is correct just in case ?

    Best Regards,
  • In reply to Ryuuichi machida:

    Hello Ryuuichi,

    Yes, 4 pixel clocks (this is tens of nanoseconds) of the allowable skew is correct. I understand that possible skew at PCB level is in picoseconds, however the devices needs to be able to correct for the cable pair-to-pair skew (which may reach few nanoseconds - still a lot of margin available).

    Regards,
    Davor

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