Part Number: DS90UB953-Q1
We are using the 953/954 SerDes with a CMOS sensor. About the 953 MIPI-CSI input, the datasheet says "Up to 4 Data Lanes at 832 Mbps Per Each Lane". This indicates a total throughput of around 3.2Gbps for 4 MIPI lanes.
I want to confirm if the above statement means the MIPI CLK can not be beyond 416MHz, or it is talking about the throughput regardless how fast my MIPI CLK is.
Considering the following scenario:
The sensor is able to provide 4K@60FPS RAW10 and has 4 MIPI lanes with a default 1.44Gbps/lane (720MHz). However we only need run FHD@60FPS RAW10. Considering the load throughput, it has around 1.2Gbps in total and 300Mbps/lane.
So using the default 1.44Gbps/lane mode, the MIPI signals will stay in Low Power after bursting out the effective data in High Speed. In this case, we have a 720MHz MIPI CLK which is higher than the 416MHz. But the effective throughput is only 300Mbps which is lower than the 832Mbps.
Does this setting work with the 953 Serializer? If not, is there anyway to overclock the 953 because our sensor vendor does not recommend us to lower the sensor clock.
Thanks in advance,
FPD-Link Systems & Applications
Training on FPD-Link Serializer Deserializer devices and system: https://training.ti.com/fpd-link-learning-center
More information on IVI or ADAS FPD-Link products: http://www.ti.com/interface/fpd-link-serdes/overview.html
In reply to Liam Keese:
In reply to Hmmm:
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