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DS90UB953-Q1: synchronous vs. non synchronuous mode

Part Number: DS90UB953-Q1

Hi,

i am a bit confused about differences between synchronouos to non-synchronous mode at 953 & 954, and some other MISC question.

can you please elaborate on differences between synchronouos to non-synchronouos mode (limitations are not clearly mentioned in datasheet):

1. which modes (synchronouos vs. non synchronous) are supported for COAX (some changes has been implemented between preliminary to non preliminary data-sheets)?

2. how does these differences impacts integration, please refer to the following topics:

3. reference clock for FPD channel, is it relevant for system developement or it should be transparent for external user?

4. 954 CSI output frequency? I understand that any of the modes impacts MIPI-CSI frequency.

5.  Is there an integration limitation that requires MIPI CSI Rx received by 953 to be synchronized to CLK_OUT pin generated by 953?

6. can you please specificly elaborate differences between synchronuous to non-synchronouos mode? according to datasheet it is mentioned that re-synchronization & extra buffering is required for non-synchronuous mode --> where & why extra buffering & re-synchronization are required for non-synchronuous mode?

7. why there is a reigster for configuration of continuous mode both at 953 & 954? as i see it configuration of 954 for continuous node is enough? where am i wrong in my assumption?

8. Which mode is required to be configured by 954 in order to support 913? Is it raw mode?

  • Hi Tomer,

    1. which modes (synchronouos vs. non synchronous) are supported for COAX (some changes has been implemented between preliminary to non preliminary data-sheets)?

     

    They are both supported. For 954, non-synchronous/coax can only be set using the 954 registers, but synchronous coax can also be configured via strap setting .

     

    2. how does these differences impacts integration, please refer to the following topics:

    3. reference clock for FPD channel, is it relevant for system developement or it should be transparent for external user?

     

    If you are referring to the refclk provided to the 954, the frequency of this clock will affect the BC rate (and therefore the forward channel rate & CLK_OUT when the 953 is in synchronous mode) as well as the CSI-2 output data rate of the 954.

     

    4. 954 CSI output frequency? I understand that any of the modes impacts MIPI-CSI frequency.

     

    The output frequency does not depend on the 953 clocking mode.

     

    5.  Is there an integration limitation that requires MIPI CSI Rx received by 953 to be synchronized to CLK_OUT pin generated by 953?

     

    This is not a requirement. The sensor can run independent of the CLK_OUT as long as the total CSI-2 lane data throughput is slower than the FPD-Link forward channel data rate. However, using the 953 CLK_OUT signal can remove the need for an additional oscillator for the sensor.

     

    6. can you please specificly elaborate differences between synchronuous to non-synchronouos mode? according to datasheet it is mentioned that re-synchronization & extra buffering is required for non-synchronuous mode --> where & why extra buffering & re-synchronization are required for non-synchronuous mode?

     

    This will depend on the user system. Often, multiple sensors are used in combination such as to create a single image. If these multiple sensors are not synchronized the processor must perform additional buffering and re-synchronization. In a single sensor system, this additional processing would not be needed. However, using non-synchronous mode always requires an additional CLK_IN reference to the 953 whereas synchronous mode requires only a reference clock to the 954.

     

    7. why there is a register for configuration of continuous mode both at 953 & 954? as i see it configuration of 954 for continuous node is enough? where am i wrong in my assumption?

     

    I assume you are referring to register 0x02 of the 953 and register 0x33 of the 954. The difference between these registers is that register 0x02 controls how the 953 processes the CSI-2 clock input (so if the sensor provides a continuous clock, this should be set to continuous) whereas the 954 register controls the CSI-2 clock output.

     

    8. Which mode is required to be configured by 954 in order to support 913? Is it raw mode?

     

    Any of the DVP RAW modes should work for the 913A and 954 combination.

    Regards,

    Zoe

                                                                                                                                                                                                                                                                       

    Training on FPD-Link Serializer Deserializer devices and system: https://training.ti.com/fpd-link-learning-center

    More information on IVI or ADAS FPD-Link products: http://www.ti.com/interface/fpd-link-serdes/overview.html

  • In reply to Zoe Nuyens:

    hi Zoe,

    Thanks for the answers.

    There is something I don't understand. 

    i don't understand why user should know about these modes? more specificly I don't understand what is the meaning of non-syncronous mode?

    As i see it, i can always set modes as synchronous and never connect the async pin.

    what am i missing? Can you please explain me differences between synchronous mode (CLK_OUT is disconnected) to non-synchronous mode?

    in other words I don't see any motivation of using non-synchronous mode --> when should we do it?

     

    Thanks,

    Tomer

  • In reply to Tomer Shapira:

    Hi Zoe,

    some further (practical) questions:

    1. I am trying to access 954 registers using I2C commands --> BCC_CONFIG register (Address 0x58), although register is mentioned as RW, for some reason i can't write to it (alwayys read default value), I2C access to most other RW registers works fine. Do i need any sequence in order to access this register? any idea what can lead this strange behaviour?
    I have suffered from the same problem when tried access 0xD5.

    2. For some reason LOCK/PASS signals are not stable (somtiemes 0 & somtimes 1), any idea what can lead to this strange behaviour? can it be related to COAX cable length?

    3. When i changed values of AEQ registers (0xD5 from F2 to 52) LOCK/PASS stability seemed to improve (addresses 0xD2 - 0xD5)? should I configure these registers?
  • In reply to Tomer Shapira:

    Hi Tomer,

     

    First, one comment on what you said. In synchronous mode, it is the CLK_IN pin that has no input (CLK_OUT may still be used).

     

    Generally, synchronous mode is the preferred mode. This mode is included to provide flexibility to customers and for ease of use for customers used to non-synchronous mode.


    For the practical questions:

    1. Please make sure you have configured port selection (954 register 0x4C) before reading/writing to these registers as they are port dependent.

    1. Yes, the length/quality of the cable may affect performance.
    1. You may configure these registers, but this is likely related to the issues with your link. So it can be helpful to lower the AEQ maximum for debugging purposes, but usually this is not desired in a final system as it will limit the ability of the AEQ to adjust to cable aging, etc. Resetting AEQ may also be useful in the debugging process.

                                                                                                                                                                                                                                                                       

    Training on FPD-Link Serializer Deserializer devices and system: https://training.ti.com/fpd-link-learning-center

    More information on IVI or ADAS FPD-Link products: http://www.ti.com/interface/fpd-link-serdes/overview.html

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