Hello,
In SN65LV1224B, what problem will occur if not following the procedure in Figure 21. Device Startup?
Is there a problem with the procedure to set PWRDNB to Low> High, after setting VDD to 3.0 V while PWRDNB is HIGH?
If there is no problem with this procedure, is there a regulation for the time when Low should be held in the Low> High procedure?
Best Regards,
sopatopa