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DS90C385A: Is there any solution using FPD Link

Part Number: DS90C385A
Other Parts Discussed in Thread: DS90CF386

Hello,

Our customer ask us solution.

Now, the customer connect FPGA and LCD panel using FPD Link (1 clock lane and 4 data lane) directly.

The output jitter of the FPGA is 550ps. The acceptable input jitter of the LCD receiver is 500ps.

So, it is out of spec.

The customer are searching LVDS retimers or SerDes for reduce a jitter.

The customer try to use the DS90C385A  and the DS90CF386 as follows.

FPGA------(LVDS 5lane) ----- DS90CF386 -------(Parallel 28bits)------

DS90C385A ------(LVDS 5lane) ------ LCD panel

Is it possible to use the set of the customer?

Is there any other solution with low cost? 

Best Regards,

Naoki Aoyama

  • Hello,

    We will look into this and get back to you

    Regards,
    Yaser
  • Hello,

    Is there any update?

    The customer want to know how about the output pulse position of the DS90C385A at
    pixel clock as 57.5MHz, 54MHz and 27MHz.
    Is it follow the skew margin of the LCD panel as 500ps?
    Of course, the skew is occurred due to layout.
    But now, we consider without loss of layout.

    Best Regards,
    Naoki Aoyama
  • Hello,

    The scheme you outlined of using DS90CF386 & DS90C385A as LVDS retimer/repeater can work in principle and has actually been used before. Can you please clarify the 500 ps margin? Is it +/-500 ps skew of LVDS data relative to LVDS clock?

    Regarding DS90C385A output pulse position for the frequencies you mentioned, we don't have data for these specific frequencies, but you can get approximate numbers from the frequencies already mentioned in the datasheet (e. g. for 27MHz you can use +/-450 ps, for 54MHz and 57.5MHz, it will be between +/-200 and +/-250 ps).

    Regards,
    Yaser
  • Hello,

    I checked the skew margin of the LCD panel.
    It is +/-500ps.
    It is possible to use the DS90C385A for transmitter.
    I will suggest the customer to use the DS90C385A.

    Thanks,
    Naoki Aoyama