Other Parts Discussed in Thread: DS90CF386
Hello,
Our customer ask us solution.
Now, the customer connect FPGA and LCD panel using FPD Link (1 clock lane and 4 data lane) directly.
The output jitter of the FPGA is 550ps. The acceptable input jitter of the LCD receiver is 500ps.
So, it is out of spec.
The customer are searching LVDS retimers or SerDes for reduce a jitter.
The customer try to use the DS90C385A and the DS90CF386 as follows.
FPGA------(LVDS 5lane) ----- DS90CF386 -------(Parallel 28bits)------
DS90C385A ------(LVDS 5lane) ------ LCD panel
Is it possible to use the set of the customer?
Is there any other solution with low cost?
Best Regards,
Naoki Aoyama