DS100MB203: DS100MB203 : MODE select pin description datasheet

Data_path.pdf

Hello Lee,

Thank you for the clarification.

We have used the device in our design and we are facing some issues during the bring up of the board.

I have a few more queries related to the device:

1.For the MODE pin configuration, there is 10GE option apart from 10GBaseKR.What physical medium does the device support when in 10GE mode?How is it different from 10GBaseKR?

2.In the page1 of datasheet, it is mentioned that "when operating in 10G-KR and PCIe Gen3 mode , the DS100MB203 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients". Does this mean that equalizer and DEM values of DS100MB203 will be automatically set in 10GBaseKR mode ? Or do we have to set the values manually?

3.I have attached an image with data-path in our design.In the configuration shown, the link between TLK10034 and SWITCH2 is not coming up.We have observed that when we force the switch port to 1G Mode the link is up and working.But in 10GBaseKR mode, auto negotiation is happening and the auto-negotiation bit is set in both devices.But the link goes down after that.This happens continuously and the link status is shown as ''up'' and ''down'' multiple times. The link status is not stable. We have used similar path in a design earlier , but without DS100MB203. What can cause the link status to change continuously?

4.In the DS100MB203 EVM schematic, the AC  coupling capacitors used are 0.22uF whereas in our design we have used 0.01uF. Can this be a reason for the link to not work?

TIA,

Ashitha

Hi Ashitha,

1. The device equalization is designed to support either PCB traces or copper cabling in 10GE mode.  This is the same as 10G-KR mode except the driving amplifier in 10G-KR is a "non-limiting" design.  For 10GE the voltage gain is relatively high.  For 10G-KR the voltage gain is much closer to 1:1.

2. In 10G-KR or PCIe modes the non-limiting output design allows some analog waveform information through the MB203.  This semi-transparent behavior allows the receiver to see changes in the original transmitted signal characteristics.

2a. The values are static.  They will have to be set manually.  For the channel topology shown the EQ and DEM should be set to the minimum values.

3. The link partners are not training to a good value.  With such a short channel it may be better to skip training and set manual values.

4. Some standards like SATA and SAS use 0.01uF AC coupling capacitors with 8B/10B encoding.  For 64/66B encoding I would prefer to use 0.1uF.

Regards,

Lee 

Hello Lee,

Thank you very much for the reply.

We replaced  the AC coupling capacitors with 0.1uF caps, but there wasn't any change

Now we have disabled link training and trying to bring up the device in manual mode.We are not able to find the optimum values for TLK and the link is not up.

We have a query .Is it possible to put DS100 in loopback mode (DIN to DOUT) internally?

Thanks,

Ashitha

Hi Ashitha,

I am working with an engineer to better understand the best approach with the TLK10034 device. 

There is no internal method to loopback the DS100MB203.

Just looking at the link topology and length, I would expect the MB203 settings to be relatively low EQ and DEM since the total length is ~10inches.  This would put the total attenuation in the range of ~ 10 dB. 

Do you know what the Switch2 device and the TLK device are using for Tx Equalization?

Does the link go down in both directions or just one?

What are the current DS100MB203 settings?

Regards,

Lee

Hello Lee,

The link is down in both directions.
The configuration settings of ds100 are as follows:
Reg:0x06-> value 0x18

0xF->15

0x5E->0x7

0x5F->0xFC

0x17->0xA8

0x18->0x0

0x2C->0x0

0x2D->0xA8

0x2E->0x0

The same settings are applied for Channel2-channel5 as well.

We are not sure on what are the exact values used for EQ by SWITCH2.

We have a few queries:

1. In one of our earlier board with similar datapath but without DS100, the links were coming up as expected .

The data path was PROCESSOR<->TLK10034<->SWITCH2.

In the current design with DS100, we are doubtful that since we are setting the EQ and DEM values of DS100 .Wont this active device effect the link training between SWITCH2 AND TLK10034 causing miscommunication between the two?Is this causing link to fail?

2.In one of earlier replies you have mentioned that "design allows some analog waveform information through the MB203." Can you please explain which signals will be passed transparently?

Thanks,

Ashitha

Hello Lee,

With the values suggested one channel was up.
With adjustment in Vod the other channel was also up.

But the value of the register 0xE.0x00F of TLK10034 is not stable and is continously changing.

We observed that the link is not stable and going up-down continously.

With change on Vod value  of DS100 the frequency in which the link goes down is varying.

we observed when the registers 0x2d/0x3d/0x17/0x34 are configured 0xAA, 0XA8 the frequency in which the link goes  down decreases.

What can be the cause of this behaviour?

Thanks you very much
Ashitha