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DS90UB954-Q1: Configuration for External FrameSync With Two DS90UB954 Deserializers

Part Number: DS90UB954-Q1

Hi Champs,

My customer would like to synchronize two DS90UB954 Deserializers as shonw in Figure 29 of DS90UB954 datasheet.

- Share same 25MHz and supply to REFCLK port of both 954.

- Set GPIO_0 for Backchannel FrameSynch, and supply external Frame Synch to both 954.

- Configure FS_CTL as 0x80 (External FrameSync from GPIO0)

- Configure BC_GPIO_CTL0 as 0x8A ( BC GPIO1=fixed low, BC GPIO0=FrameSynch)

With above setting, customer's board doesn't work properly.

Could you check if there is missing configuration?

Best regards,

Nobuo Fujihara

  • Hello,
    Can you explain what they are seeing? What is the back channel rate set to (BC_FREQ_SELECT)?
    Is the FS_SINGLE bit set to '1'?
  • Hi,

    Is there anymore info you can provide other than the customer board not working properly? Did you set Register 0x10 (GPIO0_PIN_CTL0)? You can write 0x91 to this register to enable external framesync and enable GPIO0 (Refer to Table 7 of the DS90UB954 Datasheet). Please ensure that you are also selecting the correct port (Register 0x4C) and set the Back Channel Config (Register 0x58) to the appropriate settings.

    I would recommend trying to get just one pair of the 953/954 working before using external framesync with 2 954s as the next step to debug.

    Regards,
    Jonny

    ______________________________________________________________________________________________________________________

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  • Thanks for your support.

    So far customer is reconsidering hardware setup and register configuration.

    I will close this thread once.

    Regards,