We are using a TLK2501 to interface to Virtex5 RocketIO.
In the direction of RocketIO transmitting to TLK2501, we are having problem synchronizing the 2 SerDes. On the Xilinx side, we configured CoreGen to use 8b10b and have full control idle characters and data.
We suspect somehow we are not driving the idle patterns expected by TLK2501 but haven't figured out why. If anyone can share any insight, we'd really appreciate it.