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TLK2501 interface to RocketIO

Other Parts Discussed in Thread: TLK2501

We are using a TLK2501 to interface to Virtex5 RocketIO.

In the direction of RocketIO transmitting to TLK2501, we are having problem synchronizing the 2 SerDes.  On the Xilinx side, we configured CoreGen to use 8b10b and have full control idle characters and data.

We suspect somehow we are not driving the idle patterns expected by TLK2501 but haven't figured out why.  If anyone can share any insight, we'd really appreciate it.

  • Hello Ching Yu,

    It is possible to code an FPGA to interoperate with the TLK2501.  One word of caution is that the FPGA must be programed to create the coded data stream including IDLE creation *exactly* as the TLK2501 does.  Any 8b/10b data stream that creates IDLEs differently than the TLK2501 will cause an error upon decode at the TLK2501 receiver.  The TLK2501 lifted the IDLE creation from the IEEE802.3 specification exactly as defined in table 36-6 in the IEEE (IEEE802.3) specification.  That is, the IDLE sequence is a K28.5 D5.6 if the initial running disparity before the IDLE is positive; else the IDLE is a K28.5 D16.2.  There are no exceptions to this.  Anything else and the TLK2501 will flag the word as an error.  The TLK2501 does not generate all of the possible valid K codes in the coding tables, just K28.5 and the K codes used in Carrier Extend and Error Propagation which was borrowed from the IEEE802 GMII definition.  Basically, if the TLK2501 receiver sees anything that could not have been generated by a TLK2501 transmitter then it will flag it as an error.   A TLK2701 or TLK2711 might be more interesting as a more general purpose 8b/10b SERDES.  These devices dropped the TX_EN and TX_ER pins and instead make them K-code control pins for the whole 8b/10b coding space, including all valid K codes. I hope that helps.


    Thanks,


    Atul Patel