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clock recovery circuit
Related Posts

  • Forum Post: What happens in TLK1501 RX if the RX data would be input without GTX_CLK?

    Atul Patel
    Kobayashi-san, The reference clock to the PLL ( called GTX_CLK on the TLK1501) must be present for the device to operate, even if the device is being used only for the receiver portion. There is one PLL in the SERDES device, and this PLL supports both the transmit and receive functions. The...
    on Mar 16, 2010

  • Forum Post: slk 2501 clock problem

    Nikola Vranic
    Hello, I have design like on picture and all what I want is to make loop thourgh FPGA. Problem is that I have 1 oscillator for each slk2501 chip which are slightly different (clk 2 - clk 1 =~ 11 Hz for STM1, and ~1MHz for STM4) which result empty or full FIFO in FPGA. Please, how to setup TX...
    on Dec 6, 2010

  • Forum Post: DS90C241 to SN65LVDS150 ?

    Rainer Seidel
    Dear all, I´m Rainer from Hamilton Sundstrand Germany. Some time ago, colleagues did a board for analog data acquisition with a DS90C241 24:1 LVDS serializer to output a continuous stream of measured values. In my current project I`m going to collect these data from up to 20 such sources...
    on Mar 16, 2012

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