High Speed Interface

Forum Post: RE: TUSB 7320 PCIE endpoint Configuration

ELIAS VILLEGAS — Fri, 24 May 2013 22:03:00 GMT

Hello,

The TUSB7320 is a PCIE endpoint but is is always configured by the Operating system which already has the xHCI driver, ultimately you will need to create your own driver or follow the xHCI spec to configure it.

Regards.

Forum Post: RE: HDMI/DVI Intra-pair and Inter-pair skew

Mark Sauerwald88474 — Fri, 24 May 2013 21:56:00 GMT

Two resources that have more info, and guidelines are:

Channel Link I design Guide: http://www.ti.com/lit/ml/snla167/snla167.pdf

LVDS Owners Manual: http://www.ti.com/lit/ml/snla187/snla187.pdf

Mark Sauerwald

Forum Post: RE: FPD Link III - DS90UB914 wake up in the wrong mode

Dac Tran — Fri, 24 May 2013 18:33:00 GMT

Hi Matthias,

Thanks for the clarification. Sorry I may have confused the modes. So for 12 bit LF mode, the Rmode configuration is 0Kohm or zero voltage at the MODE pin. Measure the voltage level at the MODE pin to ensure there is no voltage/ground offset. Disconnect the serializer and read the DES register 0x1F=00.

To clarify, the PCLK ratios are related to the linerate of the FPD-Link interface and not the PCLK frequency. With an external PCLK applied the ratio of PCLK is 1:1 from SER PCLK input to DES PCLK output. For example your PCLK is 12MHz; it will be 12MHz on DES PCLK output regardless of the MODE setting and only the FPD-Link linerate is divided. Unless you are running off the internal 25MHz oscillator on SER, then you will see the PCLK frequency divided by the MODE ratio on DES PCLK output.

Dac Tran

SVA APPS

Forum Post: RE: DS92LX1621 PCLK logic levels

Dac Tran — Fri, 24 May 2013 18:12:00 GMT

Hi Eric,

The 1.8V supply is only a limitation on the local oscillator option. Typically running a standalone oscillator, the DIN data sampled would be asynchronous to the oscillator clock (unless it you sync or buffer it). In most cases, you would want it fully synchronous to the pixel rate including data, HS, VS, etc.

Thanks for pointing out the errors on silkscreen markings. We will correct this on next revision.

For more comprehensive documentation on the LX16EVK01, you can refer to the SERDESUB-16USB EVM which uses the same platform -- http://www.ti.com/lit/ug/snlu100/snlu100.pdf You will also find all the pcb layers in the document.

The CMLOUTP/N loop-through output driver (pins 32, 33) on Deserializer. These are equalized data output and are designated as reserved pins. These are mainly used for signal monitoring and eye diagram tests. In default mode these are disabled but by setting bit 4 of register 0x3F to 0 you can enable this output. Signals can be accessed by the P1 connector on EVM board.

For the I2C timeouts, is this a NACK from the remote device? Do you have a plot of the failure?

Dac Tran

SVA APPS

Forum Post: RE: TUSB9261 DEMO BOARD

ELIAS VILLEGAS — Fri, 24 May 2013 15:49:00 GMT

Not sure, but it has a standard USB 3.0 Type B connector, so you need a standard USB 3.0 cable to connect it to your PC.

Regards.

Forum Post: RE: DS100MB203 - LVCMOS Input Specification

Kawai — Fri, 24 May 2013 13:59:00 GMT

Mark-san,

Thank you for your reply.

So, can I understand that DS100MB203 LVCMOS specification is Vih (MIN) = 1.7V at both 2.5V and 3.3V mode ?

It must be lower than 1.7V to interface 2.5V LVCMOS.

Could you please revise the datasheet ?

This is very much confusing.

Best Regards,

Kawai

Forum Post: RE: The issue of the use of DS90UB913/914.

Jeong Yeun-Gwon — Fri, 24 May 2013 02:30:00 GMT

Hi.

Answer is late.

LCD screen broken phenomenon occurs with non-periodic.

CAMERA BOARD with LCD BOARD connection within 10 seconds or more than 20 minutes over time:

And irregular.

LCD Screen Flashing, screen vibration, Video ON/OFF in the occurrence of such phenomena.

1. Split this into two halves, the top and bottom of the image.(Lcd tearing).

2. Screen vibration.

3. Screen on/off .

4. Vsync waveform.

5. Rosenberger cable used.

Thanks you.

Forum Post: TUSB9261 .bxl bug

kaiyu lin — Thu, 23 May 2013 20:58:00 GMT

Hi! I tried to obtain footprint and schematic library for Altium with Ultra Librarian from your .bxl file.

During generation process it gives the following error:

"unexpected : ."

How can I solve this problem?

Thank you!

Forum Post: RE: DS90CR288 split to multiple DS90CR287

Jim Suriano — Thu, 23 May 2013 19:21:00 GMT

I have verified that our PWR DOWN signal is being pulled low during the startup period and goes high after the clock is good and available. I'm still looking for suggestions on how we might fix this issue. I can post relevant parts of the schematic if that would be useful.

Forum Post: RE: LMH1982 Evaluation board software

Mark Sauerwald88474 — Thu, 23 May 2013 15:04:00 GMT

John

Please contact me directly at mark.sauerwald@ti.com for further assistance with this issue.

Mark Sauerwald

Forum Post: SN65LVCP408

ayusman mohanty1 — Thu, 23 May 2013 13:56:00 GMT

Hi Max, David

I am also facing a similar issue. I am planning to use SN65LVCP408 with a 3G-SDI receiver in my system in a 8 input and 4 output configuration. I am planning to connect them in AC coupling mode so that the Common mode voltage requirements will be taken care of. However I am seeing that the output voltage differential swing ranges of SN65LVCP408 do not match with the input voltage differential swing of receiver.

The datasheet of SN65LVCP408 mentions that the output differential swing range is from 1000 - 1500 mVpp. Whereas the receiver input differential swing range is from 500-1100 mVpp.

Can anyone please help me out in resolving this issue?

I am in the closing phase of my design and any quick help will be really appreciated.

Regards

Ayusman

Forum Post: SN65LVCP408 Compatibility issues with 3G-SDI receiver

ayusman mohanty1 — Thu, 23 May 2013 08:28:00 GMT

Hi,

I am planning to use SN65LVCP408 with a 3G-SDI receiver in my system in a 8 input and 4 output configuration. I am planning to connect them in AC coupling mode so that the Common mode voltage requirements will be taken care of. However I am seeing that the output voltage differential swing ranges of SN65LVCP408 do not match with the input voltage differential swing of receiver.

The datasheet of SN65LVCP408 mentions that the output differential swing range is from 1000 - 1500 mVpp. Whereas the receiver input differential swing range is from 500-1100 mVpp.

Can anyone help me out in resolving this issue?

I am in the closing phase of my design and any quick help will be really appreciated.

Regards

Ayusman

Forum Post: RE: DS50PCI402 Spice or IBIS model available

Manoel Barros Marin — Thu, 23 May 2013 08:02:00 GMT

Hello,

I would like to simulate with Hyperlynx the PCIe x4 transmission lanes of a board that we are designing.

The board can be equipped either with the DS50PCI402 or the DS80PCI402 and the PCIe connection is through cable.

I was looking for the model of these components when I read this post where John Goldie offer this models but through a direct contact.

I have sent an email to John Goldie but I receive an error that the email can not be delivered.

Could you please, share this models with me or the email of the person in charge of this?

Thank you.

Forum Post: RE: LMH0387 Launch amplitude Fine Control Resister(02h, 6:3)

TKOB — Thu, 23 May 2013 03:07:00 GMT

Gary, thank you very much for your help. I understood the resister and the function.

Forum Post: RE: 3G Test Equipment Question

Mark Sauerwald88474 — Wed, 22 May 2013 23:44:00 GMT

This is the correct forum.

Anything is possible. I am not familiar with the Evertz 5601MSC, but Evertz make very good quality gear. We do have a Phabrix SX in our lab here, and have never had issues with the signals that it produces.

Do you have a WFM such as the Tek WFM8300? - It may be that there is something in the ANC space of one or the other that is confusing the monitor, and you could see if there was a difference with the WFM.

Forum Post: RE: How to transmit a 36bits + 4bits at 148.5MHz (from example HDMI 225MHz ADV7106) to FPGA XILINX 5 pairs LVDS DDR

Mark Sauerwald88474 — Wed, 22 May 2013 15:01:00 GMT

Here are a couple of thoughts on how this might be done. What you choose will depend on what you want to do with the data at either end...

There is a Broadcast video standard (SMPTE 424) which supports the transmission of HD over long lengths of coax cable (up to ~200m) - it runs at a serial rate of 2.97Gbps per each cable, and is typically handled as a 20 bit pixel (4:2:2 sampled) at 148.5 MHz word rate. There is another standard (and I forget the number) which allows two such links to be synchronized, thus allowing for 5.94Gbps to be transported over two coax cables.

TI supports this standard with a broad variety of products which you can see at www.ti.com/sdi - particular parts which may be of interest are the cable equalizers such as the LMH0394, and the LMH0340/LMH0341 SerDes pair.

If the distance is not very great, you can use the SerDes that is available within the Kintex and Artix FPGAs, to generate a single serial link at 6Gbps- and use the TI signal conditioning products like the DS125RT410 This part is a 12Gbps equalizer/Retimer/De-emphasis driver, which can operate at sub harmonics, so it will lock to the 6 Gbps stream that the Kintex is generating. Depending on the transmission medium, I would expect this to work over distances of a few meters.

Forum Post: RE: DS32ELX0421 / DS32ELX0124 SerDes

Mike Wolfe — Wed, 22 May 2013 01:39:00 GMT

Hi,

Can you provide more information about your system? Do you have SMBus access? It would be helpful if you can provide schematics, so that I can better understand your system.

Please also describe the configuration of these devices and detail the length and type of media you are trying to communicate across. Also, please list the input clock frequency you are using.

The more information you share, the easier it will be for me to help you.

Mike Wolfe \ DPS APPS

Forum Post: RE: DS90C187EVM

Mike Wolfe — Wed, 22 May 2013 01:36:00 GMT

Hi,

Let me know if you have any questions.

Mike Wolfe \ DPS APPS

(Please visit the site to view this file)

Forum Post: RE: DS100DF410 - Recommended Programming Sequence for SMBus Slave Mode

Michael Hinh — Tue, 21 May 2013 22:24:00 GMT

Hi,

The first step is to write to control registers shown in table 3,4. For example set register 0xFF to 0x0C, which would select all channels and write to the registers simultaneously, all reads target the channel 0. There is no waiting time needed. Then write to the specific registers of the channel shown in table 5; there is no ordering. For example just write to register 0x2D bit [2:0] to set the output VOD amplitude.

Regards,

Michael

Forum Post: RE: DS100MB203 use for 3:1 switching and buffering

Michael Hinh — Tue, 21 May 2013 21:38:00 GMT

Hi,

Did a search and found the SN65LVCP404, but it is up to 4.25G.

The tr/tf looks fast enough, but not rated for 5G.

http://www.ti.com/product/sn65lvcp404

Regards,

Michael