TCA9617A Issue

Jim CHEN

Expert 4795 points

Other Parts Discussed in Thread: TCA9617A

My customer use TCA9617a for 100kHz SMBUS between CPU and DDR4 DIMM.

But the CLK waveform is wrong as below:

After they try to replace this device with NXP PCA9617ADPJ, the problem was gone.

Please help to give some comments.

Thanks.

----------------------------Update 2016.10.13----------------------------------

over 7 years ago

0 Jonathan Valdez over 7 years ago

TI__Genius 16430 points

Hello Jim,

I'd be glad to look further into this. Can you provide a clearer waveform of the input and output so that I may see both sides of the I2C buffer in both cases (NXP and TI).

The schematic looks good to me, so I'm not sure what the issue is at the moment.

It would be helpful to include a SDAA & SDAB waveform on the same plot, so I can easily see the input and output of the buffer.

0 Jim CHEN over 7 years ago in reply to Jonathan Valdez

TI__Expert 4795 points

Hi Jonathan,
Please see my above update.

Thank you

0 fhoude over 7 years ago in reply to Jim CHEN

TI__Genius 17205 points

Hello Jim,
I have a few questions for you. I was wondering why the timing and duty cycle was so different from the NXP vs TCA waveforms? What data rate are they trying to achieve? Are they adhering to min low times outlined in I2C specs?
-Francis Houde

Interface

Interface forum

TCA9617A Issue