Hello -
I am working writing to the TCA9548A device using a generic i2c master interface, in which I transmit data in the order of: <SlaveAddr=0x70> <MemAddr=0x70> <DataByte=0x02>. I know that I don't need to send a separate MemAddr to this particular part, but I'm keeping this field intact so that this module is more generic for other applications in which I need a separate i2c memory address. The actual bus cycle is shown in the JPG below. Running SCL @ 400kHz.
It looks like the TCA9548A is latching the MemAddr byte as the data, as opposed to the DataByte. This behavior conflicts with the datasheet which, on page 17 under Section 8.5.4 (Control Register) says that the last byte transmitted is latched as the data. All bytes are acknowledged by the Slave, so it doesn't look to be a data integrity issue. Am I doing something else wrong?
Blue: SDA
Green: SCL (buffered on scope @ 3.3V)