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TCA9548A: Connecting TCA9548A to multiple TCA9539 devices

David Mannion
Prodigy 20 points
Part Number: TCA9548A
Other Parts Discussed in Thread: TCA9539, TCA9539-Q1

　

Hello,

　

We are designing a new system that has, among other things, an FPGA connected to a TCA9548A i2c switch device.

The FPGA is directly connected to the SCL and SDA pins of the TCA9548A.

　

The SC2 and SD2 pins of the TCA9548A are connected to SCL and SDA pins of two (_0, _1) TCA9539 devices

See sketch below.

　

 

                                +--------------------+

                                |                    |

  FPGA             9548A        |      9539_0        |      9539_1

+-------+       +------------+  |    +---------+     |    +---------+

|    SCL|<----->|SCL      SC2|<-+--->|SCL    p0|-->  +--->|SCL    p0|<--

|       |       |            |       |         |          |         |

|    SDA|<----->|SDA      SD2|<---+->|SDA    p1|-->  +--->|SDA    p1|<--

|       |       |            |    |  |         |     |    |         |

+-------+       +------------+    |  +---------+     |    +---------+

                                  |                  |

                                  +------------------+

The FPGA is the i2c master.

We want to configure:

the ports (p0, p1) of the TCA9539_0 as outputs and

the ports (p0, p1) of the TCA9539_1 as inputs.

　

We would like your feedback on the steps below.

　

1 The FPGA sends a sequence of data to the 9548A to enable channel 2 of the 9548A.

　

2 Then the FPGA sends data to the 9548A to access the 9539_0:

to configure all of the 9539_0 ports (p0:p00-p07, p1:p10-p17) as outputs driving a fixed value of 1.

　

3 Then the FPGA sends data to the 9548A to access the 9539_1:

to configure all of the 9539_1 ports (p0:p00-p07, p1:p10-p17) as inputs.

　

4 Then the FPGA will read the p0 and p1 input registers of the 9539_1.

　

We think we can keep the control register, in the TCA9548A with a fixed value to enable channel 2 (SC2, SD2).

　

On page 24 of the TCA9539-Q1 document (SCPS254B January 2014 revised April 2016),

figure 28 shows a scenario of SDA serial data to read a register.

　

Is this scenario of reading a TCA9539 register, by the FPGA master, possible through a 9548A?

　

It appears in figure 28, that the master (FPGA via the 9548A) would need to transmit the "grey" bits and received the "white" bits.

　

Is this possible with the FPGA communicating through the 9548A to the 9539_1?

　

If it is possible, what would be the specific steps (bit details) for the FPGA master to read a register in the 9539_1?

　

　

Thanks in advance.

Dave

  • 0
    TI__Mastermind 49040 points

    Hey Dave,

    Just to be sure I understand correctly, do you plan on having two TCA9539 on the same channel in parallel? The picture you drew for me looks like the TCA9539 are in series with each other where p0 and p1 of 9539_0 act as SDA/SCL lines. In the case where they are parallel, this is okay (assuming you gave them different addresses) but in the case where they are in series it will not work because it would take multiple bytes to change the outputs.

    As such, I will answer assuming you set the IO expanders in parallel.

    -----------------------------------------------------------------------------------------------------------------------------------------------------------------------

    "1 The FPGA sends a sequence of data to the 9548A to enable channel 2 of the 9548A."

    -Okay　

    "2 Then the FPGA sends data to the 9548A to access the 9539_0:

    to configure all of the 9539_0 ports (p0:p00-p07, p1:p10-p17) as outputs driving a fixed value of 1."

    -You'll need to set the output registers to all be high first then set the configuration registers to be outputs　

    "3 Then the FPGA sends data to the 9548A to access the 9539_1:

    to configure all of the 9539_1 ports (p0:p00-p07, p1:p10-p17) as inputs."

    -No need if it was just powered on, as they will be default as inputs. You can still do this step if you'd like but you don't have to.　

    "4 Then the FPGA will read the p0 and p1 input registers of the 9539_1."

    -Okay

    --------------------------------------------------------------------------------------------------------------------------------------------------------------------

    "Is this scenario of reading a TCA9539 register, by the FPGA master, possible through a 9548A?"

    -One note: FPGA's output must have open drain architecture or be able to be configured to have it.

    -Now, I assume you are asking if there are any issues with talking to an IO expander which is in series with an I2C switch. I do not see a problem as long as you make sure there are no conflicting addresses.                                                    

    TCA9548A possible addresses:                                  

    TCA9539 possible addresses:

    From the table above you can see that it is possible to have common addresses and you need to be careful not to select the same addresses for all three of your devices. Each must be unique.

    "If it is possible, what would be the specific steps (bit details) for the FPGA master to read a register in the 9539_1?"

    Register address will depend on which ports you want to read from. 0x00h for port0 and 0x01h for port1. The example above shows 1 byte being read and then a NACK to end the transaction however if the master ACK'd instead then you would read the next byte in the register. So if you first chose register 0 and didn't initiate an ack with a stop, then the next byte would be data from register 1. This is due to the auto increment function and will repeat the register pair over and over until a NACK and stop condition is given. (you will continuously read input ports 0 and 1 until you NACK and stop). You can see an example of this in figure 33 of page 25 of the TCA9539.

    -Bobby

  • 0 in reply to BOBBY
    Prodigy 20 points

    Thanks for the reply Bobby.

     

    Yes, the two 9539 devices are in parallel.

    All three devices (9548, 9539_0, 9539_1) have unique addresses.

     

    Regarding my step 2 below, looking at table 3 “Command Byte”, the POWER-UP DEFAULT value of Output Port 0 and Port 1 is all ones (high).

    Therefore, since I want p0 and p1 to be outputs driving high, then all I need to do is configure those ports to be outputs.

    I don’t need to set the output port values to be high first (they already are) before I set the configuration registers to be outputs (value 0x00).

    Is that correct?

     

    Regarding my step 4 below, they key thing is for the FPGA to tri-state the SDA in order to read the response from the 9539_1 via the 9548A.

     

  • 0 in reply to David Mannion
    TI__Mastermind 49040 points

    Dave,

    "I don’t need to set the output port values to be high first (they already are) before I set the configuration registers to be outputs (value 0x00).

    Is that correct?"

    -The output registers bits are default as 1's which I expect to mean they are all high. I think it is safe to assume all you need to do is set the configuration registers to be outputs (0x00).

    You should note that the write function also will have the auto increment function in it meaning you don't need to do a stop condition and set the configuration bits separately but can do it with 4 bytes (slave address->Command Byte->data into configuration register0->data into configuration register1).

    You can set configuration registers separately if you wanted to though. (6 bytes of data required though)

    --------------------------------------------------------------------------------------------------------------------------------------------------------

    "Regarding my step 4 below, they key thing is for the FPGA to tri-state the SDA in order to read the response from the 9539_1 via the 9548A."

    -I think I understand what you are asking here but correct me if I'm wrong. You want to know if you will read the correct value (either SDA pulled low or SDA is high) when you are reading data because the FPGA input is in floating high-Z mode. This should not be a problem, in the case where SDA is high you will just see the pull up voltage and when low you should effectively see a voltage divider between the pull up resistance and the drain to source resistance of the FET pulling down.

    The only mode of concern is if the PFET is on (FPGA pushing high) and tries to pull up the SDA line, the voltage divider from the PFET's drain to source resistance and the transceiver's NFET drain to source resistance during an ACK could cause issues with the FPGA seeing a NACK. (May also damage the FETs if too much current is drawn.)

    I hope this helps,

    -Bobby