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TCA9545A: issue

Shu-Cheng LIN
Guru 11785 points
Part Number: TCA9545A

Hi Sirs,

We use SMBus switch TI/ TCA9545APWR for memory in our project Oceancat.

In some of case we found BMC couldn’t read memory’s SPD information.

The TCA9545APWR power well VCC is +2.5V_SPD_DUAL and RESET is +2.5V_DUAL, the sequence is +2.5V_DUAL=>+2.5V_SPD_DUAL.

The SMBus CLK and DATA trasmited from FPGA to memory pass through the switch(TCA9545APWR).

We measure waveform of the DDR_SDA, DIMM_ABC_SDAR and SMB_DDR_RST# in Pass planar and fail planar as below screenshots, please refer to it.

It show that the timing of SMB_DDR_RST# de-assert in fail planar is short than pass planar.

Please help us to check will the spike cause RST pull low earlier to result any abnormal behavior, and any sequence between VCC and RESET#

Thanks!!

  • 0
    TI__Mastermind 49110 points

    Hello Shu-Cheng,

    Could you clarify for me what the Blue, pink, and green waveforms are? The picture is a bit blurry; I think pink is DIMM_ABC_SDAR, green is SMS_DDE_RST#, and blue is DDR_SDA.

    "Please help us to check will the spike cause RST pull low earlier to result any abnormal behavior"

    -I haven't seen issues with our TCA line switches causing glitches when pulled high for a short time.

    -Reset being pulled low for a minimum of 6ns would reset the switch, which your waveform doesn't show it being pulled low when communications start. You may want to try pulling RESET high a little bit earlier before you begin communication (wait a small amount of time after turning on 2.5_SPD_DUAL before trying to communicate).

    "any sequence between VCC and RESET#"

    -There isn't a sequence required for Vcc and Reset but there is a requirement for Vcc. This is covered in section 11 of the datasheet. The parameter you care about most will likely be the rise time which needs to be between 0.1ms to 100ms. Though this is fairly easy to hit.

    -Bobby