Part Number: MSP432P401R
I'm writing to a TCA9548A over the I2C bus using a MSP432P401R as a master. The write is the standard start bit followed by the
seven address bits 0x70 followed by a 0 (low) for a write. At this point I expect a ACK from the TCA9548A and get one about
26mS later which is then followed by the data 0x01 (which should enable channel 0) , followed by an ACK and a STOP.
While this seems to be working, when reading back the control register data it read 0x00 and when testing the I2C bus
on the channel 0 output it is not connected through the TCA9548A chip to the output.
1. Is the 26 ms delay of the first ACK an valid example of clock stretching?
2. Are there any things to be aware of when using the TCA9548A (this is a TI chip), i.e. why would it ack but not connect to the output?
