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TCA9546A: TCA9546A Pass gate voltage vs Vcc

Part Number: TCA9546A

Is there an app note explaining the internals of the Mux operation.

The Vcc should me less than or equal to the min VDD pull up voltage. But I don't understand why.

Also, what is the gate voltage of the internal FET pass gate?

  • Hi Hitesh,

    I'm not aware of an app note on this topic, but I can try to explain the device's operation to you. I'm not in the office at the moment, but I will get back to you on Monday.

    Max
  • Hey Hithesh,

    I can confirm with Max we do not have an app note discussing this. We do have an article online written by one of our engineers which discusses this briefly here:

    "The Vcc should me less than or equal to the min VDD pull up voltage. But I don't understand why."

    Internally we have an NFET between the channel and main SDA/SCL lines which isolate the two voltages on the source and drain pins of each channel. If you remember, NFETs will begin to move from the cutoff region of operation into the linear/saturation once the gate to source voltage falls below Vth. 

    So lets assume you have a channel pulled up to 5V and Vcc of the switch also at 5V. On the main SDA/SCL lines you have 3.3V and the Vth of the FET is 0.7V. In this case one side (the source) is now below the gate voltage minus Vth. This means we are now conducting and there is essentially a voltage divider between the two pull ups rather than isolation (this is what we want). Both sides will basically see about the middle point between 5V and 3.3V which is about 4.15V below.

    If we redo this scenario where the gate voltage follows 3.3V instead of 5V then we can see the following:

    Minor leakage current shifts the main line and slightly pulls the channel line dow by 0.01V but isolation is provided which is exactly what we want. This is because now neither side of the FET is below the gate voltage minus the Vth voltage.

    I hope this explanation makes sense to you.

    "Also, what is the gate voltage of the internal FET pass gate?"

    -This should be the Vcc voltage you apply to the device.

    If you are still confused, do not be a afraid to reach out,

    -Bobby

  • So the goal is to keep the FET off when Voltage is High and turn it ON when the Voltage drops to Low.

    To keep FET turned OFF, the Vcc (= gate voltage) should be equal or lower than the lowest pull up voltage.

    In the second Ckt above, if Vmain line goes from 3.3V to 0V, the FET starts conducting and the Vch line capacitance discharges thru the FET, correct?

    Q1: What happens when Vch line goes from 3.3V to 0V?

    Q2: When a channel, let's say Vmain transitions from 0V to 3.3V, the FET is ON from 0V to 2.6V(3.3V minus FET threshold 0.7V) and OFF from 2.6V to 3.3V? What is the impact of this. On Vch side, would the waveform look like its being driven from 0 to 2.8V and then Rpull-up would take over till 5V depending on bus capacitance? 

  • Hey Hithesh,

    "So the goal is to keep the FET off when Voltage is High and turn it ON when the Voltage drops to Low."

    -Correct, if the channel is selected then you want the voltages to be isolated from each other until a low ("0") is passed.

    "To keep FET turned OFF, the Vcc (= gate voltage) should be equal or lower than the lowest pull up voltage. "

    -Technically it can be Vcc-Vth in order to keep the FET in the cutoff region. So it can be a bit lower than the lowest Vcc and still work.

    "In the second Ckt above, if Vmain line goes from 3.3V to 0V, the FET starts conducting and the Vch line capacitance discharges thru the FET, correct?"

    -Yes, you are correct.

    "Q1: What happens when Vch line goes from 3.3V to 0V?"

    -Such as in an ACK or when it is told to transmit data? Then the low or zero is also passed to the main line. You can think of the FET as two FETs with their sources tied to each other. By doing this the FET has no dedicated "source or drain." Either side can be a source or drain. The example below shows two NFETs which now can act to pass signals both ways without nonideal body diodes conducting.

    "Q2: When a channel, let's say Vmain transitions from 0V to 3.3V, the FET is ON from 0V to 2.6V(3.3V minus FET threshold 0.7V) and OFF from 2.6V to 3.3V? What is the impact of this. On Vch side, would the waveform look like its being driven from 0 to 2.8V and then Rpull-up would take over till 5V depending on bus capacitance? "

    So when the main channel hits 2.6V the pass FET will stop conducting (now in cut off region). At this point both sides will be at similar voltages.  Once cutoff occurs, the Vch will have it's voltage being dictated by the pull up resistor and the parasitic capacitance and the same goes for Vmain.

      

    In the real world, this simulation does not work out perfectly though, as the drain to source resistance changes with the drain to source voltage and there can be multiple slew rates. This problem can become quite complicated as there are two FETs (one pulling down) and one pass FET which have constantly changing drain to source resistances.

    Thanks,

    -Bobby

  • Thanks for the explanation.

    The 464uV and the 306uV in the figs above is the voltage drop because of the RDS_ON of the FETs?

    Didn't get the last statement though-

    "This problem can become quite complicated as there are two FETs (one pulling down) and one pass FET which have constantly changing drain to source resistances."

    For the case when Vmain drops from 3.3V to 0V, FET T2,T1 are OFF initially and T2,T1 turn ON when Vmain is 1.9V(T2 source=Vmain+0.7v diode drop=2.6V) and remain ON till 0V. Correct?

    I am not sure about FET turn on/off when the drain voltage changes. It's easy with Source Voltage changing. It's just Vgs.

    The Turn ON is initiated because of the T1 body diode, right?

    In the fig below, when Vch drops from 5V to 0V, the FET T1 is OFF till Vch hits 1.9V?

    When Vch is 2.6V, Vmain is still 3.3V because of the body Diode (assuming diode drop is 0.7V).

    T1 turns ON when Vch is 1.9V and Vmain is 2.6V and stays ON till 0V.

    Is my understanding correct?

    But when Drain goes from

  • "The 464uV and the 306uV in the figs above is the voltage drop because of the RDS_ON of the FETs?"

    Correct, this is the steady state voltage drop across the FETs.

    "Didn't get the last statement though"

    There are two FETs in operation when I2C is involved with this pass FET (the Master/Slave pulling low and the pass FET). FETs can be thought of as voltage controlled impedances. When we talk about the actual waveforms this comes into play as the voltages across the FETs change over time and will change the slew rates on the pull down action as well as the pull up action. It's easy to think of if we talk about steady state but the actual transient response is difficult.

    "For the case when Vmain drops from 3.3V to 0V, FET T2,T1 are OFF initially and T2,T1 turn ON when Vmain is 1.9V(T2 source=Vmain+0.7v diode drop=2.6V) and remain ON till 0V. Correct?"

    My example removes the body diodes (this is needed if we want to pass lows to BOTH directions). If the body diode was present (if I only used one FET) then this simulation would not of worked. The issue of the body diode is more of a problem when Vgate is zero. In this case, the FET should be high impedance (theoretically infinite) and basically look like an open circuit. This means the channel is disabled. The issue of the body diode is when the source is greater than the forward voltage of the body diode, the FET will conduct through its body diode when source voltage is larger than the drain voltage by a minimum of the forward conducting body diode. You can see an example of this below when I simulate a pull down on both sides while the gate is referenced to GND.

    ^this means even with the FET referenced to GND, a low can still pass from one side to another. This is unwanted behavior which is why I used two FETs in my previous post.

    To reiterate, the body diode is a problem when the gate is off. When the gate to source voltage is greater than Vth then the body diode can be ignored because it is seen as a high impedance path compared to the drain to source.

    ^no voltage drop across FET due to diode can be seen above.

    "The Turn ON is initiated because of the T1 body diode, right?"

    No, I think I may have confused you about the body diode. Hopefully the information above clears it up.

    "In the fig below, when Vch drops from 5V to 0V, the FET T1 is OFF till Vch hits 1.9V?"

    No, it'll conduct once it's below 2.6V like the other side. See below:

    You can see below the body diode is ignored:

    Thanks,

    -Bobby

  • How does the FET conduct when Drain Voltage drops to 2.6V.

    In the Fig below, how does the Source Voltage also become 2.51V when Drain is at 2.51?

    Is it because of leakage current thru the FET?

  • Hey Hithesh,

    I think there are two points of confusion here.

    1) Wrong thought: A FET's pins are predetermined to be a source and drain. They cannot be interchangeable and current can only flow in one direction.

    -This is not true. The source and drain is essentially just referenced to the two pins. When either pin drops below the gate voltage by Vth then you can call the pin which current is entering the drain and where current is leaving is referred to as the source. With this understanding, then either side can be the source or the drain.

    This can be understood in how the device is made, the source and the drain are both mirrors of each other and ideally exactly the same. This difference is when a FET is made, there are actually two body diodes attached to the body but makers will short one side. In the case with an NFET the side with the short is essentially called the source and there is now equivalently only one body diode from the source to the drain because the other was shorted. Remember: FETs originally have two body diodes and 4 terminals (one being the body substrate).

    So now to answer the question:

    "Is it because of leakage current thru the FET?"

    No, the source is now on the Vch side while the drain is on Vmain side because: Vchx<Vg-Vth

    2) Confusion: The Body Diode of a FET

    The issue is the body diode which can conduct current in one direction (unwanted non ideal problem) when the gate voltage is zero OR if Vth and the forward conducting voltage of the body diode are largely different (if Vth is greater than Vdiode). The body diode can typically be ignored if Vth is less than the forward conducting voltage of the body diode when the Gate voltage is larger than Vth.

    This means we can ignore the body diode when:

    Vg>Vth AND Vth=<Vdiode

    This was shown in all my previous examples because Vth~=Vdiode=700mV

    Below is when this is not true, where I change Vth to be 2V and Vdiode is constant at about 700mV (dependent on current as well).This means Vg>Vth BUT Vth>Vdiode. So if Vchx<Vmain-Vdiode AND Vchx>Vg-Vth then we will see unwanted conduction.

    The lower picture shows an example when Vg>Vth AND Vth>Vdiode but now Vchx<Vg-Vth. This means the body diode is ignored and Vchx acts as the source.

    Thanks,

    -Bobby

  • Thanks again. That clarifies a lot of confusion.

    The interchangeable source/Drain would not apply if I used an external Mosfet to do the level conversion. Correct?

  • Hey Hithesh,

    "The interchangeable source/Drain would not apply if I used an external Mosfet to do the level conversion. Correct?"

    No, FETs drains and sources are mirrors of each other. The image below shows how FETs are NPN/PNP junctions. They can be interchangeable as a result.

    Notice that when you have an PN junction that is also a diode and a NP junction forms a diode as well. These diodes connect to the body pin of the FET. Below shows the four terminal FET with the diodes (not shorted yet).

    Thanks,

    -Bobby

  • Thanks again.

    There are plenty of articles on the net that mention body diode conduction. Below is just one by a major I2C vendor -