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TCA6424A: part holds data line low during a read operation

Craig Barker
Prodigy 60 points
Part Number: TCA6424A
Other Parts Discussed in Thread: TCA9548A

Sometimes during a read operation, the TCA6424A will take the data line low while the clock is high (violates I2C spec), and hold it low indefinitely.  It takes a RESET or power cycle to recover.  Any idea what could be causing this?

The master stops sending clocks once the data is taken low during a clock high state.  i don't know if this is per I2C spec, or due to the master implementation.

Craig

  • 0
    TI__Mastermind 49370 points
    Hey Craig,

    What other devices do you have on the I2C bus?

    Do you have scope shots of your communication with the TCA6424A during the read operation when this occurs that you can provide?

    Is it possible for you to send 9 clock pulses on the clock line after this occurs to see if SDA unlatches?

    Thanks,
    -Bobby
  • 0 in reply to BOBBY
    Prodigy 60 points

    Hi Bobby,

    This is the only device on this bus.  We are using a TCA9548A I2C switch between the master and this device and this channel is the only channel enabled. 

    The Master is a PIC18LF66K40T.  This master controls the 9 clocks for reads and writes in the HW and is not controlled by the FW.

    This first picture shows the two byte write command to write the address, then the two byte read command.  The last byte is terminated when the slave drives the data line low during a clock high.  I don't know why the master stops sending clocks in this case.

    This next picture is another instance more zoomed into the terminated read byte.  This time a few more bits are clocked before the slave drives the data line low while the clock is high.

    Thanks for your help.

    Craig

  • 0 in reply to Craig Barker
    TI__Mastermind 49370 points

    Hey Craig,

    Just to be sure, when this happens can you probe the other SDA channels and see if any of those channels are also latched low? I'd like to make sure the other channels are indeed disabled.

    I would also like to check to see what happens when you reset the TCA9548A switch while the SDA line is latched. Does the main channel with the master's SDA remain latched low or does the SDA for TCA6424A device stay low? This will help confirm that the TCA6424A is the one that is latching low and that this is not a coding issue.

    I would also like to try pulsing the clock signal 9~18 times to see if the SDA line unlatches.

    In regard to your waveforms, I don't see anything that jumps out at me. It looks like the pull up resistor is correctly sized. There is some very minor coupling between SDA and SCL but it doesn't look like it affects the signal integrity.

    What does seem odd is the master stops sending clock pulses during the latching so I am wondering is this is related to code instead. Typically the master only looks for an input from the slave during the ACK phase or when receiving data from the slave and continues to send clock pulses during all cases...

    It may also be helpfully if you include schematics for us to review (pull up resistors, voltages used, and including the switch and devices connected to the switch if we have not ruled out the possibility of the channels being disabled).

    Thanks,
    -Bobby

  • 0 in reply to BOBBY
    TI__Guru 62910 points
    Hi Craig,

    I just wanted to check in - have you been able to resolve this? Or, have you had a chance to look into Bobby's feedback?

    Max
  • 0 in reply to Max Robertson
    Prodigy 60 points

    Max,

    I haven't been able to try all of Bobby's suggestions.  in fact, Most of them I cannot try as the HW on our Microcontroller controls the clock line and it is not under FW control.

    I know that only one of the devices is holding the SDA line low, as when that device is disconnected (connector is removed) from the bus, the bus begins operating again.

    Once I can get back to looking at this full time again, I will post any more info that I generate.

    Craig