• Resolved

TLK10232: 10G in 1:1 mode with 156.25 MHz Refclk and Data Rate = 3.125Gbps

Part Number: TLK10232

Hi all,

I'm using the TLK10232 in a 1 to 1 mode, with 156.25 MHz Refclk and 3.125Gbps Data Rate.

I used the Bring Up Procedures (v.2) PDF to initialize the device (p. 21).

When reading the 1E, F register ("CHANNEL_STATUS_1") I see that the 6th bit is always high, indicating that the an overflow has occurred in the transmit data path (CTC) FIFO.

This happens when either sending K28.5 or data.

The LS side is connected to a CYCLONE (ALTERA) FPGA's transceivers and using the same data rate and the same reference clock.

The transceivers in the FPGA encode and decode the data to the 8b/10b form (as in the 1:1 mode, this is not done in the TLK10232).

We see that some of the packets are sent OK but a lot of the time we see that we receive a "9C" symbol (K28.4), maybe indicating an error in the system, maybe the overflow that we see in the "CHANNEL_STATUS_1" register.

What might be wrong with this setup?

Are there any configurations that are needed, in addition to those that are described in the Bring Up Procedures (v.2) PDF?

  • Hi Andrei,

    Are you using optical fiber, copper or backplane?

    On the other hand please try these procedure:

    Device Pin Settings o Ensure ST input pin is Low.
    o Ensure MODE_SEL input pin is High.
    o Ensure PRBSEN input pin is Low.
    o Ensure REFCLK_SEL input pin is Low
    • Reset Device o Issue a hard or soft reset (RESET_N asserted for at least 10 us -or- Write 1’b1 to 30.0.15)
    - Disable Auto-Negotiation. Write 0x2000 to 0x07.0000
    - Disable Link Training. Write 0x0000 to 0x01.0096
    • Mode selection o Write 4’b0111 to 30.2.3:0 to set HS PLL multiplier to 10x o Write 2’b01 to 30.3.9:8 to set HS_RATE_TX to Half Rate o Write 3’b101 to 30.3.2:0 to set HS_RATE_RX to Half Rate o For 1:1 mode ƒ Write 2’b11 to 30.1.13:12 to set mode ƒ Write 2’b00 to 30.7.9:8 to set LS TX Serdes lane rate to Full rate ƒ Write 2’b00 to 30.7.1:0 to set LS RX Serdes lane rate to Full rate
    • Issue Data path Reset o Write 1’b1 to 30.14.3
    • Wait for 1000ms

    As well, would you mind to send me the values of register CHANNEL_STATUS_1?

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • In reply to Luis Omar Moran:

    Hello Luis,

    Thank you for your response.

    1.I'm using an optical fiber. The same card works well in 10GBASE-KR Mode.

    2.I have tried your procedure and it didn't help.


    first read : 0x340

    all next reads: 0x1743

    4.My initialization for TLK:

    { 0x1E,0x0000,0x8000}, //GLOBAL RESET (p. 41 of TLK DS)
    { 0x07,0x0000,0x2000}, //Disable Auto-Negotiation
    { 0x01,0x0096,0x0000}, //Disable Link Training
    { 0x1E,0x0002,0x8357}, //set HS PLL multiplier to 10x, VCO runs at lower end of frequency range(also i have checked higher end of frequency range)

    { 0x1E,0x0003,0xA94D}, //set HS_RATE_TX and HS_RATE_RX to Half Rate
    { 0x1E,0x0001,0x3000}, //set mode 1:1
    { 0x1E,0x0006,0xF115}, //set LS PLL multiplier to 10x
    { 0x1E,0x0007,0xDC04}, //set LS TX and LS RX Serdes lane rate to Full rate

    { 0x1E,0x0004,0x6500}, // Serdes Rx precursor equalizer selection : 13/9 cursor amplitude (p. 45 of TLK DS). EQ[14..12] = 6. ENTRACK[15] = 0
    { 0x1E,0x0008,0x0100}, // Adaptive LS_EQ (p. 50 of TLK DS)

    { 0x1E,0x0005,0x2000}, // change to PRE emphasis[7..4] = 0. POST CURSOR[12..8] = 0
    { 0x01,0x00AB,0x0001}, // Enable FEC

    { 0x1E,0x000E,0x0008} //Issue Data path Reset

  • In reply to Andrei Ginzburg:

    Hi Andrei,

    For XAUI-to-SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 auto-negotiation and 10G link training. To do this, follow this procedure:


    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)

    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).

    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12

    4. Disable link training by writing 16’h0000 to 0x01.0096

    5. Write 16’h03FF to 0x1E.8020.  This allows the link settings that would normally be configured through KR training to be configured manually instead.

    ***6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004.  For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.  This can be a starting point, but you may need to do some BER testing to optimize the values.

    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.


    The RX settings must still need some type of adjustment. This is where you have to spend time during those settings until it’s (mostly) error free when the Link Training feature is disabled.

    HS_SERDES_CONTROL_1/2/3 (not 4 since that’s pre-emphasis, only for copper links not optical).


    Focus first on:






    Best Regards,

    Luis Omar Moran

    High Speed Interface

    SWAT Team

  • In reply to Luis Omar Moran:

    Hello Luis,

    Thank you very much for your support so far.

    I think that there was a misunderstanding, the card works now in 10GBASE - KR mode but I need it to work in 10G mode (1 to 1 mode, with 156.25 MHz Refclk and 3.125Gbps Data Rate).

    After TLK initialization I read the CHANNEL_STATUS_1: 0x1743.

    • HS_AZ_DONE = 1,
    • HS_AGC_LOCKED = 0,
    • HS_CHANNEL_SYNC = 1,
    • LS_PLL_LOCK = 1,
    • HS_PLL_LOCK = 1

    When I write 0x1 to 0x1e.0004, bit 6 ("HS_PEAK_DISABLE"), "HS_AGC_LOCKED" changes to 0x1 ("CHANNEL_STATUS_1" is 0x1F43)

    What do you suggest we do next?

  • In reply to Andrei Ginzburg:

    Hi Andrei,

    Sorry for the delayed response. For 10G General Purpose, please set the device in this mode. Please make sure link training and auto-negotiation are disabled. Then, select the SERDES PLL Multiplier for 3.125Gbps data rate.

  • In reply to Luis Omar Moran:

    Hi Luis,

     I have found the problem. 

    My card has two source clocks for the 156.25 Mhz: one for the FPGA and one for the TLK10232,

    because of that we always receive TX_FIFO_OVERFLOW = 1,

    I configured the TLK ref clock to REFCLK1P/N which is connected to the FPGA.

    Now the FPGA and the TLK works with the same clock and everything is now OK.

    Thank you for your support.