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Part Number: UCC21520EVM-286
I have to develop a board with half-bridge.
The upper side is P-MOS (FQD3P50), the lower is N-MOS (IRFR420).
Lower side is connected to GND, upper to +440V.
The output of this bridge is connected to 50Ω throw +220V polarized decoupling capacitor in order to obtain bipolar pulse (±220V).
The half bridge has to produce this pattern ...
To drive this half bridge I buy a demo board UCC21520-286.
Because I need short rise/fall time (theoretically less than 1ns) I insert no resistance between drive output and mos gate and I use no death time (DT pin 6 is connected to VCCI).
I supply 18V to VDDB,VDDA from isolated DCV01015P (I use no bootstrap supply for nigh side).
I substitute R13,R12 (2.2Ω) with short.
I parallelize C16 with another one 10uF ceramic capacitor and C15 with two 10uF ceramic capacitor.
When I set-up 8 pulse with less or equal than 60ns duration pulse-train begin to corrupt ... here the image
PUT A PICTURE WITH DRIVER OUTPUTS
To understand the problem I modify demo board UCC21520EVM-286 in this way.
I solder 1.5nF ceramic capacitor as CL_B (that absorb 1.5nFx15V=22.5nC every edge equivalent to IRFR420 19nC Miller-Plateau charge).
I supply 18Vto VDDB.
I generate train pulse to INB input by function generator.
When I set 8 pulses 105ns of positive/negative duration (210ns of period) the driver work properly. Here the waveforms.
When I reduce the width to 60ns (120ns of period) I observe randomly missing pulses at the end of the train.
If I disconnect the capacitor (no load to the output) the signal is perfect.
If I solder RL_B = 24Ω and CL_B=0Ω (short circuit) the output OUTB of the driver is OK. I notice that last pulses are shorter than initials.
If I reduce RL_B (for example to 22Ω) last pulse became more short until it disappear.
If I freeze the IC this problem gets worse. If I reduce VDDB this problem improves.
I am an applications engineer supporting this product. I will help you to figure out this behavior.
Once these questions have been answered, that should help to find a starting point for the issues you are experiencing.
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In reply to Derek Payne:
In reply to Mauro Fantina:
I apologize for the delay. I have replicated the behavior in our lab. It does not seem to be related to UVLO, since the supply voltage is maintained and there is a restarting period of approximately 50µs after UVLO condition clears. I will refer this description and my own replication results to our design team, and get back to you as soon as we have more information about why this behavior occurs.
For now, looking at your application, I can make some recommendations to work around this behavior:
Gate Driver Applications Engineering Manager
Dallas, TX USA
Updating with new information:
It seems that the high frequency operation, combined with the high supply voltage, is affecting the stability of the internal channel regulators, which reduce VDD to a level suitable for supplying the internal logic blocks of the driver. When these regulators becomes unstable, the gate drive logic cannot function correctly, so some pulses become corrupted. This does not trigger UVLO because the UVLO circuit monitors the voltage from VDD to VSS, which remains greater than the threshold. As the supply voltage decreases, the regulator stability should improve. If you cannot get the short pulses you need with 10V or 12V, or if you must use 18V supply voltage to VDD, UCC21520 will not be able to meet your application requirements.
Some other options to consider:
Still, I do not know if any TI gate drivers can support the switching frequency you require. I think you may need a very special gate driver to handle a signal this fast – maybe an “RF MOSFET driver” or equivalent.
I try to use 10V but it's not the solution.
I read UCC21520 datasheet but I not like tPWD (pulse width distortion) that is 1..20ns (remember my pulse are 30ns width).
See § 8.12 at page 13
About UCC27531 and UCC27517A I'm afraid about the same problem ...
Here's UCC27531 ...
Here's UCC27517A ...
So I think to evaluate GaN drivers ... thanks for your support
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