UCC21520EVM-286: Suspect UVLO of one output

Part Number: UCC21520EVM-286


I have to develop a board with half-bridge.

The upper side is P-MOS (FQD3P50), the lower is N-MOS (IRFR420).

Lower side is connected to GND, upper to +440V.

The output of this bridge is connected to 50Ω throw +220V polarized decoupling capacitor in order to obtain bipolar pulse (±220V).

The half bridge has to produce this pattern ...

To drive this half bridge I buy a demo board UCC21520-286.

Because I need short rise/fall time (theoretically less than 1ns) I insert no resistance between drive output and mos gate and I use no death time (DT pin 6 is connected to VCCI).

I supply 18V to VDDB,VDDA from isolated DCV01015P (I use no bootstrap supply for nigh side).

I substitute R13,R12 (2.2Ω) with short.

I parallelize C16 with another one 10uF ceramic capacitor and C15 with two 10uF ceramic capacitor.

When I set-up 8 pulse with less or equal than 60ns duration pulse-train begin to corrupt ... here the image



To understand the problem I modify demo board UCC21520EVM-286 in this way.

I solder 1.5nF ceramic capacitor as CL_B (that absorb 1.5nFx15V=22.5nC every edge equivalent to IRFR420 19nC Miller-Plateau charge).

I supply 18Vto VDDB.

I generate train pulse to INB input by function generator.

When I set 8 pulses 105ns of positive/negative duration (210ns of period) the driver work properly. Here the waveforms.


When I reduce the width to 60ns (120ns of period) I observe randomly missing pulses at the end of the train.

If I disconnect the capacitor (no load to the output) the signal is perfect.

If I solder RL_B = 24Ω and CL_B=0Ω (short circuit) the output OUTB of the driver is OK. I notice that last pulses are shorter than initials.

If I reduce RL_B (for example to 22Ω) last pulse became more short until it disappear.

If I freeze the IC this problem gets worse. If I reduce VDDB this problem improves.


3 Replies

  • Hello Mauro,

    I am an applications engineer supporting this product. I will help you to figure out this behavior.

    • I notice that some of your waveforms did not make it into the post, could you please repost these waveforms along with their descriptions?
    • In your schematic, do you have the DT pin programmed, bypassed to VCCI, or floating?
    • Is OUTA active at any point during these measurements?
    • Is there noise present on INA or on the DIS pin which could result in the driver temporarily becoming disabled?
    • Are you measuring directly at the pins of the IC using tip-and-barrel?

    Once these questions have been answered, that should help to find a starting point for the issues you are experiencing.


    Derek Payne

    Texas Instruments

  • In reply to Derek Payne:

    * the waveforms are now OK except driving signals for IRFR420 and FQD3P50 because I have to remount board ...

    *DT is stuck to VCCI (see picture in the post)

    *OUTA is floating

    * INA is connected to FPGA Cyclone Altera EP4CE15F17C8 out pin programmed to GND throw 33Ω

    * I observe no particular noise on DIS, INA pins when pulse disappears

    * I measure using ground loop method NO tip-and-barrel
  • In reply to Mauro Fantina:

    Hello Mauro,

    I apologize for the delay. I have replicated the behavior in our lab. It does not seem to be related to UVLO, since the supply voltage is maintained and there is a restarting period of approximately 50µs after UVLO condition clears. I will refer this description and my own replication results to our design team, and get back to you as soon as we have more information about why this behavior occurs.

    For now, looking at your application, I can make some recommendations to work around this behavior:

    • Operate VDD at 12V or less. You reported (and I have verified) that reducing the VDD supply improves short pulse performance. There is also little benefit to operating the MOSFETs in the schematic at a higher voltage, based on their datasheet profiles.
    • Make sure the rise and fall times of your input and output waveforms are very clean and sharp. The 30ns pulse width is getting very close to the minimum 20ns specified in the datasheet, and delays in the rising and falling edges of your input signal could be enough to cause trouble. Consider using impedance controlled traces and proper termination near the INA/INB pins in the end application layout. The input signal path lengths must also be matched.
    • Keep the gate drive loop extremely short, with very low inductance between gate and source. Place local bypassing directly at the supply pins of the output drivers, on the same layer, with no vias or other layout features interrupting the current path from capacitor to IC pins.


    Derek Payne

    Texas Instruments