TLK10034: TLK10034 :10GBaseKR Autonegotiation and Link training

Part Number: TLK10034

3124.Data_path.pdf

Hi,

Flow of data is as shown in the attached document.

DS100 and tlk10034 are in 10GBaseKR mode.

The DS100 settings for channel are as follows:

Register ->Value:

0x0f->0x0

0x17->0xa8

0x18->0x0.

With these values the 10GBaseKR link is up.But the register CHANNEL_STATUS_1 (0x1E.0x000F) of TLK10034  read as 0X5D03 and 0x5C03 . The value is not stable and oscillating between the two.The bit  HS_DECODE_INVALID is getting set frequently. What causes this bit (HS_DECODE_INVALID) to get set?

Can changing any register of TLK prevent this ? Is there any threshold setting which can be altered to increase the margin so that decode invalid will not be set frequently?

Thanks,

Ashitha

4 Replies

  • Hi Ashitha,

    Can you please check HS_ERROR_COUNTER register (0x1e.0x10)? Also, are you sure the HS_LOS (bit 13 of 0x1E.0x000F) doesn't get set?
    HS_DECODE_INVALID indicates that the decoder received an invalid code word, or a 8b/10b disparity error. There is no threshold setting or margin to increase to prevent this error from being set.

    Regards,
    Yaser
  • In reply to Yaser Ibrahim:

    Hi Yaser,

    The HS_ERROR_COUNTER keeps incrementing till we clear it.
    HS_LOS bit is not getting set.

    We observed the following as well.
    When we tried to change the settings as mentioned in the document "SLLA351– December2014" [section 5, page number 10] using register 00x01.0x9001, The ENTRACK bit was not changing.How to enable this functionality?


    Thanks,
    Ashitha
  • In reply to ASHITHA A V:

    Hello,

    Have you tried to write 1 to bit 15 of HS_SERDES_CONTROL_3 (0x1e.0x0004) to force track mode?

    Regards,
    Yaser
  • In reply to Yaser Ibrahim:

    Hi Yaser,

    We have wrote 1 to HS_SERDES_CONTROL_3 register and we are able to set the ENTRACK bit. With the following settings in TLK10034 , sometimes the link was up and stable.Also the HS_ERROR_COUNTER read '0'. But sometimes the link is unstable and the error counter overflows.
    We have set the following registers in TLK10034:
    0X1E.0X004->0X9400
    0X1E.0X8020->0X40;

    Since the link is becoming stable we think that there may not be signal integrity issues.
    But why is the link not stable with the same settings that worked earlier ?
    Once the link is stable, it remains in that state till it is powered down.

    Thanks,
    Ashitha