I hope this is the right place to post this question. If not, please let me know where to go next.
This part is used in a basically unterminated configuration. There is a series resistor (each 590 Ohms) on each input; also, between each resistor and each input to the part, there's a transzorb connected to ground. It's a very low frequency application and the cable is only a few feet long. I believe the driver is a DS26LV31 but I'm not sure. (In the lab, I used an Agilent 8116A pulse generator.)
There's errant behavior in one installation of this part. It's going to a Vo = L state with an open circuit on the inputs*. It's an intermittent that can't be duplicated; it seems to be happening randomly and only after long periods of operating normally. In one case, it seemed that shorting the input* caused it to go to the V0 = L state after removing the short.
So, I continued trying to come up with a way to reliably induce the failure.
Just for information (I know a certain range of common mode voltage on both pins with the pins shorted is an area of concern with this part) I tried driving the + side of the pulse generator into both inputs*. (The pulse generator and the part have common grounds.) With this configuration, and varying the amplitude of the input from 5V to 1V (10Vpp wrt ground), the part's output was at a constant "L" state for a certain range of input amplitude. So, I tried the same test on another installation (an installation that hasn't exhibited the random failures described above) of the part and there were no cases of amplitude that resulted in a constant "L" on that part's output.
Any ideas what might be going on here? Just a failed part that has failed in a rare mode? Any suggestions for other tests to try?
* input: input to the inline resistors, not the part's input pins
It seems like the Industrial Interface forum might be the right place for your post (I'm not 100% sure...). Let me move it there for you.
Audio Applications Engineering Manager
Dallas, TX USA
the DS26LV32 is a differential receiver which detects logic states based only on the differential input voltage, Vid, and NOT with regards to ground. Its input sensitivity is +/- 200mV which means for the receiver output to go High the input voltage at RI+ must be 200mV more positive than the input voltage at RI- and for the receiver output to go Low the input voltage at RI+ must be 200mV more negative than the input voltage at RI-. Any Vid in between those values will cause undetermined output states, meaning the output might be High or Low or might even toggle.
Tolerances in device manufacturing can lead to slight deviations in the input attenuators as well as in the hysteresis of the internal differential comparator between devices.
Thus applying 0V Vid to the inputs of one receiver might yield a Low, while applied to another receiver might yield a High. In the test setup you are describing you are applying 0V Vid to each tested receiver. Therefore your measurement results are plausible.
I suggest using failsafe biasing as shown in the application section of the data sheet. Thus when the driver should go high-impedance, you will always have a defined Vid at the receiver input. Since you explained that your application is only a few feet long and operates at low data rates you might not need a 100 ohms termination and thus your failsafe biasing network could have some higher impedance, such as 3 x 4.7k resistors.
Also the 590 ohms resistor before the transorbs are not clear to me. When the transorbs conduct they are supposed to divert high currents to ground. You don't want to limit the current before the transorb but after the transorb. Depending on the type of transorbs, they can develop a clamping voltage that is higher than the maximum specified input voltage of 14V. In this case you want to limit the current into the device inputs. Also when expecting high transient overvoltages you want to look into MELF resistors or high-voltage resistors as the standoff voltage for normal SMD resistors is often limited to 200V.
just want to mention you don't need the middle 4.7k resistor. It's a habit of mine using 3 resistors for failsafe biasing which only makes sense if the middle resistor is your termination resistor. However in your case you simply need to pull the A and B lines up and down respectively.
The driver's signal level is RS485 & the differential driver device used is a 5962-9076502MFA.
I'm trying to find out if the driver has a bias circuit. According to the RS-485 thread on Wikipedia, that's a common/acceptable practice.
My circuit actually has 2 receivers connected as shown in the picture here. When everything is working properly with V1 = V2 = logic 1, Vin = + 380 mV with a DMM. When the phenomenon occurs, one of the outpus goes to logic 0 (fail), the other remains at logic 1 (good). Unfortunately, I didn't get a Vin reading for the case when the failure is occurring.
Could one chip's bias circuits be supporting the other chip's failed (or marginal) bias circuits via their connections shown in the diagram?
I'll separate the receivers and gather some more voltage information.
firstly, please change the location of your input resistors. Apply them past the Transzorbs as I suggested in my previous schematic.
The check whether the phenomenon still occurs.
The transzorbs were placed at the part's input pins to provide overvoltage protection for the part. The resistors were placed before the transzorb to provide overcurrent protection for the transzorbs.
1) You protect Tranzorbs with MOVs and Pulse resistors, not just ressistor.
2) For your application choose 400 W to 600 W TVS diodes such as SM712. The Pulse robust 10-ohms resistor are placed in front of the receiver to limit current flowing into the device should the internal ESD structure ever conduct.
Good luck, Thomas
We measured ~ -380 mV at the input to a single-receiver* circuit (Vin+ wrt Vin-) with the pins open-circuited; which results in a logic '0' at the receiver's output. In another instance of the single-receiver circuit, we measured ~ +380 mV under the same conditions.
We don't know if it's a defective receiver or transzorb. We're returning it to the manufacturer for analysis and repair.
* single-receiver means half of the diagram I posted earlier
With the rest of the circuit disconnected, the open-input failsafe feature should read with a positive differential input across the inputs due to internal high impedance pull up and pull down path. The +380mV sounds right. The minus is not expected, and thus the reason for the output low as it is below the threshold. If the device is measuring this, it has likely been damaged by EOS / ESD and can be sent for FA. If however, this -380mV differential is seen in-circuit, then the external components should be reviewed to see what is impacting the bias to pull it low on that channel / device.
John GoldieDPS APPS / SVA / www.ti.com
What are the terms for an FA?
Also, a general forum usage question: What is the function of the green "Verify Answer" button on each post?
Your local sales support person can assist on the FA policy and where to return a part to. In general upon receipt the unit is retested and also inspected to see if some level of damage such as an ESD event has occured to the device. A report of the findings is generated and provided.
I couldn't find the expected open-circuit voltage across the inputs in the DS26LV32AT spec sheet. I know it should be a positive voltage but is there a minimum voltage magnitude I could look for in future testing?
You are correct, it is not a datasheet parameter, I would look for >+200mV differential (above threshold limit). Pulls are weak current sources and are expected to vary somewhat over PVT thus not directly spec'ed.
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