There is an errata for the TL16C752B chip about the Rx timeout. Would this errata apply when FIFO is enabled, but DMA Mode is 0?
1. Problem: The TL16C752B UART correctly generates a character timeout interrupt (if IER0 set) when theserial input (RX) has gone quiescent (continuously high) for more than four character times. The problem isthat if a new character is received after the timeout, the interrupt will be cleared. The interrupt will begenerated again if another timeout occurs. This is an error because reading the RHR (RBR) should be theonly clearing mechanism for this interrupt.Work Around: If software is responding to an asserted INT and a read of the IIR reports no active interrupt,then assume it is caused by a new byte being received. Check the LSR; if LSR0 (DR) is set, read the RHRand repeat.Severity: Moderate
The errata applies to byte mode (DMA Mode 0) as well as to FIFO mode (DMA Mode 1).
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