Hi,
I am facing a strange interrupt loop on a TL16C550DPFB
reading the IIR we get 0xC4, reading the LSR we get 0x60 repeatedly , this put our driver in an endless loop
the logic of our driver is while there is IRR&1 !=0 , if IRR&0xf=4 -> while LSR&1 read fifo
This cause an endless loop.
Do you know any reason why we could end up at this state? IRR=0xc4, LSR=0x60?
Thanks and best regards
L
Hello Laurent,
What receiver trigger level do you have set in the FIFO control register, FCR[7:6]?
Does this happen on more than one system?
Are you meeting the timing requirements for reading the RX FIFO? The minimum time between reading the RX FIFO and reading the status registers (IIR and LSR) is 425 ns.
Do you see the actual interrupt pin go high when the IIR is reading 0xC4?
Can you provide more of the interrupt handling routine? You can post it here in the forum or send it directly to my email, jfockler@ti.com.
From the code logic you provided above I see no obvious reason that LSR would continually read 0x60 in this situation unless the data is read out of RX FIFO before reading the LSR status register in the interrupt routine.
Best Regards,
Joe