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DP83620 transformerless Phy-Phy connection

Other Parts Discussed in Thread: DP83620

Hi

I'm trying to connect a DP83620 phy transformerless to another phy. Currently I have weird signal on DP83620 TXD signal pair.

Found the AN-1519 document, which describes such an application with DP83848 PHYTER.

Does this AN also applies to the DP83620?

 

regards, Marco

  • Marco,

    The DP83620 can operate without a transformer.  The application note does apply to the DP83620. 

    What does the transmit signaling from the DP83620 look like?  Could you share some scope shots and schematics showing the connections?

    Patrick

  • Hi Patrick

    Please find attached schematic and measurements. I also added a measurement of the exactly same phy-configurations but with transformer connected.

    7776.phy to phy - schematic.pdf

    2112.Transformerless phy to phy - measurements.pdf

  • Marco,

    The DP83620 VREF resistor sets the primary bias for the device.  This resistor should be 4.87 kOhms, but is shown as 4.7 kOhms in the schematic.  Could you correct this value and re-test?

    What are the trace impedances of the TD and RD lines on the PCB?  How are they laid out?

    Could you provide a datasheet for the 100nF AC coupling caps being used?

    How was the measurement with the transformer made?  Was it wired into the board somehow?  Was the measurement made with the transformer and with the AC coupling caps?

    Patrick

  • Patrick,

    Agree, the resistor value is wrong in schematic. I changed the value to 4.87 kOhms before I made the measurements.

    Meanwhile I made some progress. According to the attached application note, I inserted just 1 Pullup resistor per line. Instead of 25Ohm I used 16Ohm. Now the communication works. It seems, that the voltage levels where to high.

    But I'm still curious about the waveform of the DP83620 TX output. The Signal doesn't have the 3 states as the TX Signal of the other PHY. Do you have any explanation for this?

    The measurements with transformer were done on a properly routed pcb. This pcb was the start for the transformerless test...

     

    1362.short distances.pdf

    0383.graphs.pdf

  • Marco,

    The connection shown in the application note is a DC coupled connection.  This is not recommended.  The connection needs to be AC coupled.  For the DP83620 side of the connection, the termination resistors need to be 50 Ohms to the 3.3V supply. 

    In a transformer implementation, the DP83620 transmitter will pull current out of the transformer and through the termination thereby pulling the voltage below the supply.  Due to the transformer action, the other transmit pin will swing above the supply by the same amount. As a result, the three level signaling can be viewed differentially or single-ended. 

    Without the transformer, when one transmit pin pulls down, the other pin will not swing above the supply.  In order to view the full three level signaling when operating without a transformer, you will have to view the signals differentially. 

    Patrick

  • Hi Patrick

    The last post is more than 2 years ago but a question about the signal of DP83620 Transmitter (without transformer) rose up in meantime.
    At the beginning of the thread you mentioned the application note AN-1519 does apply to the DP83620. Figure 8 Shows 100Mb/s waveform with no transformer. In my application I just can't see this three Level signaling at the transmitt Output of DP83620. --> see measurements earlier in this thread.
    Does AN-1519 really apply to DP83620 or do I still have an error in schematic?

    I assume the LAN9221 does have a Problem with the waveform of DP83620 Transmitter, due to the higher DC bias than 3.3V.
    Is there any possiblity to get the three Level signaling with no transformer?

    regards
    Marco

  • Marco,

    I moved your post to the Ethernet forum so that it gets visibility from the experts.

    AN-1519 does apply to the DP83620. The DP83620 does support operation without a transformer. Do you have an updated schematic you can share? Are you able to read the DP83620 registers to confirm the configuration?

    Patrick
  • Patrick

    Please find the affected part of the schematic in attachement. In the word-file you find some measurements of different signals.
    Currently I don't have direct access to Register of PHY because the PHY is controlled directly by the EtherCAT IP-Core in FPGA.
    Which Registers would be of interest in your opinion?

    Marco

    Measurements.docx

    schematic.PDF

  • Marco,

    Register access would be helpful to confirm the basic configuration and status. Specifically, it would be good to confirm that the DP83620 is linked and operating in 100M full-duplex with fiber disabled.

    The transmit signaling from the DP83620 appears to be two level signaling rather than three level signaling as expected. This could occur if the RX_ER pin is being pulled low during initialization.

    I also notice that the device is configured for MII mode, but some of the MII signals (CRS, COL, TX_CLK) are not shown as connected to the MAC. Is this intended?

    Patrick
  • Patrick,

    The DP83620 is used in an EtherCAT application with Beckhoff EtherCAT IP-Core in FPGA. MII Interface is connected as required by IP-Core. CRS, COL and TX_CLK are intentionally not connected.
    Basically the communication works, with rarely Errors on the Receiver side (LAN9221). Therefore the 100M full-Duplex seems to work. I guess the Problem is the two Level signaling. I try to check RX_ER pin during reset and get Register Access.

    Marco

  • Just checked the active Speed with the Signal of the LED_SPEED. This pin indicates 100M communication. Additionally I measured pin RX_DV while reset. RX_DV is high until RESET_N is going high -> After approx. 2us RX_DV changes to low.

  • Marco,

    Did you check the RX_ER pin during reset? This is the pin that would strap fiber mode.

    What is the state of the EC_P0_nRESET pin during initialization? Is this pin not well controlled? Typically, additional components on this pin are not necessary. One concern I have is that the 0.1uF capacitor on this pin could be impacting the reset functionality. Could you remove this capacitor?

    Patrick
  • Patrick,
    It's a typo, I measured the RX_ER pin during reset instead of RX_DV.
    EC_P0_nRESET looks good and steady and is released as soon the EtherCAT IP-Core is ready. According to measurements and datasheet, the IP-Core doesn't configure the phy trough MII. --> no communication at all while I measured.
    Also removed the capacitor on the reset-Signal... no Change.
    According to my measurements the phy is configured correctly with it's strap Pins , but no MLT-3 waveform is generated due to missing transformer.
    Do you see still a Chance, that the phy is in FX mode? Does the measured waveform fit to FX mode?

    Marco
  • I checked again the configuration of the phy. Phy is definitely configured in 100BASE-TX-Mode, by pin strap Options. There is no configuration on MDIO Interface.
    Additionally I forced the phy to FX-mode for a test. In this mode the communication didn't work at all, as expected.
    Despite the application note AN-1519, DP83620 just doesn't generates MLT-3 signals without transformer.
    I appreciate any further advises on this problem.

    regards, Marco