• State Resolved
  • Locked Locked
  • Replies 7 replies
  • Subscribers 32 subscribers
  • Views 1455 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

ISO7241CDW for SPI, D channel doesn't support high signal rate?

Lebing Jin
Intellectual 390 points
Other Parts Discussed in Thread: ISO7241C, ISO7241M, ISO7841

Hi!

I am using an ISO7241CDW to isolate an SPI bus. I have two DSPs in the setup, one works as master, the other works as slave. They talk to each other via SPI bus. My problem is that it seems D channel doesn't support the SPI speed higher than 4Mbps, but in the datasheet, it says 25Mbps. When I set the SPI speed higher than 4 Mbps, channel A,B,C are ok, slave DSP can receive correct data, but the master DSP received messy data, lost many bits. When I set the SPI speed lower than 4 Mbps, all the channels work fine. 

I have the SPI bus connected to the ISO7241 chip as follows:

Both EN1 and EN2 are tied to their respective VCC pins, non-isolate side is connected to the master DSP, isolate side is connected to the slave DSP

CLK  --- PIN 3 (INA)              PIN 14 (OUTA) --- ISO_CLK

SIMO  --- PIN 4 (INB)            PIN 13 (OUTB) --- ISO_SIMO

CS  --- PIN 5 (INC)                PIN 12 (OUTC) --- ISO_CS

SOMI  --- PIN 6 (OUTD)        PIN 11 (IND) --- ISO_SOMI

I connected 0.1uF capacitors in both side as suggested in the datasheet.

Did I understand something wrong of the isolator?

Thanks

  • 0
    Intellectual 390 points
    Does any TI employee know this problem? Thank you in advance.
  • 0 in reply to Lebing Jin
    TI__Intellectual 2200 points

    Hi Lebing,

    ISO7241C will be able to transmit 25Mbps data without any problems. However, for your SPI link to work correctly at 4Mbps, you need to ensure that the overall timing budget is met.

    The timing budget includes: set-up time of CLK to SOMI on the master DSP, two prop delays through the isolator (23+23=46ns) and clock to Q delay ISO_CLK to ISO_SOMI on the slave DSP, and any other sources of delay and mismatch. All these sources should add up to < 250ns.

    Do you know the values of these timing parameters?

    Rgds,

    Anant

  • 0 in reply to Anant Kamath
    Intellectual 390 points

    Hi Anant,

    Thank you so much for your kind reply.

    I checked the timing parameters you mentioned: set-up time of CLK to SOMI on the master DSP is 26ns, clock to Q delay ISO_CLK to ISO_SOMI on the slave DSP is 21ns, and I think I also have some software delay,should be very small. All these are much less than 250ns.

    And I also tested two DSPs without isolator, then it works fine even with 10Mbps SPI speed.

    Could it be cable or connection problem?

    Besides, I'm wondering how ISO7241 transmits 25Mbps data since it has two prop delays (23+23=46ns>40ns)?

     

    Thanks.

    Lebing

  • 0 in reply to Anant Kamath
    Intellectual 390 points

    Hi again,

    I think I've figured out the problem. In master side, SOMI reads data from slave at the fall edge of CLK, before this falling edge, SOMI data must have 26ns setup time, which means that SOMI data must valid for more than 26ns before this falling edge (half of a CLK cycle, 125ns for 4Mbps). And in the slave side, when data transmits out from SOMI, it has 21ns delay. Then we also count two prop delay 46ns(min value?).

    125ns-21ns-46ns=58ns>26ns

    so in my experiment, 4Mbps is ok, when I increased the speed higher than 4Mbps, that 125ns became less, then there was not enough setup time.

    To me it seems I can't use 7241C for 10Mbps SPI communication, am I right? Do you have other sugggestion for digital isolator?

    Thanks a lot,

    Lebing

  • 0 in reply to Lebing Jin
    TI__Intellectual 2200 points

    Hi Lebing,

    Your calculation is correct. In the worst case, two prop delays of ISO7241C add up to 84ns (42ns+42ns) for 5V operation. The number I gave you earlier (46ns) was actually for ISO7241M - that was a mistake.

    We have a new part releasing in 1st or 2nd week of next month (Feb 2015) that has a max two prop delays of 32ns (16ns+16ns). You could try that for faster data rate SPI communication. Even with that device, your timing for 10Mbps looks tight because of the high setup times and clock-Q delays. Can you program the controller to sample SOMI on rising-edge rather than on the falling-edge? That will greatly simplify your timing.

    Rgds,

    Anant

  • 0 in reply to Anant Kamath
    TI__Intellectual 2200 points

    Hi Lebing,

    I forgot to mention the name of the new device: it is ISO7841.

    Rgds,

    Anant

  • 0 in reply to Anant Kamath
    Intellectual 390 points
    Thank you for your help, Anant!