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ISO7521 , ISO7821 - behavior Glitch impulse input

Ryuji
Guru 20090 points
Other Parts Discussed in Thread: ISO7521C, ISO7821

Hello,

Our customer use ISO7521C.
However, since there are the Glitch impulse in their boards, the ISO7521C output was latched High.
Thus, there are the problem in their product.
Then I propose the ISO7821 for replacement from the ISO7521C.
They would like to evaluate the ISO7821 but they need the document which explain the ISO7821 don't latch and ISO7521C is latched high when glitch input.

Could you please share the document that exlain the difference of ISO7821 and ISO7521C if there are glitch input ?
I already propose the application note of "Digital Isolator Design Guide".
However they don't accept it due to there is no description of behavior when glitch input.
Please kindly help us.

If you can't share the document in this forum ,please contact to the following e-mail address.

asaka-r@clv.macnica.co.jp

Best Regards,
Ryuji Asaka

  • 0
    TI__Intellectual 2200 points

    Ryuji,

    As you have seen in the design guide, ISO7521C uses an edge-based architecture. That is, information is only conveyed when there is an input transition. A narrow noise glitch is nothing but two transitions occuring very close to each other. In this case, the ISO7521C recognizes the first transition, but could ignore the second transition - leading the output to be stuck in the wrong state for some time, eventually corrected by a DC-correction or watch-dog mechanism.

    ISO7821 uses continous transmission (OOK, not edge based), and responds to presence or absence of a carrier. After the glitch comes and goes, the information regarding the input state is continuously being conveyed - and the output goes to the correct state within a propagation delay. The glitch is either represented at the output or filtered out.

    I hope this explanation suffices, we do not have a formal document that discusses this behavior.

    Rgds,

    Anant

  • 0 in reply to Anant Kamath
    Guru 20090 points

    Hello Anant san,

    Thank you for your reply. I understood that there is no dogument.
    I have the some questions. Please see the attached file as waveform(P.1) and behavior figure(P.2)

    ISO7521C Latch output_20150730.pdf

    (1) Explanation of customer waveform
    Page 1 in the attached file is our customer waveform.
    Here is publick forum, I attached parts of waveform. In the waveform , we couldn't get the glitch pulse due to resolution of measurement equipment.
    In the wavefrom, the output was asserted high without input high signal, however, the output was asserted low again before input asserted low from high.
    If there is a glitch pulse only, should the waveform be kept high ?

    I must explain the customer waveform. Thus, please help.


    (2) Narrow pulse
    If there are the narrow pulse, we should add the LPF.
    Could you please let me know cut off frequency of LPF when we add LPF?
    Should we eliminate the pulse witihn 20ns ?

    (3) Page2 of attached file.
    I described that the behavior. Is my understanding in the attached file correct?

    Best Regards,
    Ryuji Asaka

  • 0 in reply to Ryuji
    TI__Intellectual 2200 points

    Ryuji,

    I have replied to an email thread regarding the same questions.

    A cutoff frequency with a 15ns to 20ns delay will take care of the glitch issue.

    Your understanding shown in Page 2 is completely correct.

    Rgds,

    Anant