DS32ELX0124: About the register setting of EQ

Hi team,

 My customer is evaluating communication between
 DS32ELX0421 and DS32ELX0124 on a prototype now.
 Please let me ask you two questions about the register setting
 for EQ0 just in case.

 Q1) Is the RXIN0 EQ0 disabled when the bit5 of 0x63 is set to 0?
        In the evaluation result of my customer,it seemed that the setting values
        of 0x61 bit7:5 were effective regardless of the value of 0x63 bit5.

 Q2) Is it necessary to set the bit7 of 0x61 to 0 when EQ0 is used?
        In the evaluation result of my customer,it seemed that the bit7 of
        0x61 needed to be set to 0 in order to enable the bit6:5 of 0x61.
         *When the bit7 of 0x61 was 1,it seemed that the EQ0 did not work correctly.
  
 Please let me know if you need any additional information.
 
 Best regards.
 Tsuyoshi Tokumoto