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TLK10232: 10GKR HS ERROR

Part Number: TLK10232

Hi,

We use TLK10232 chip in the following configuration:
(1) LS_side
    Altera FPGA (XAUI 3.125MHz 4lane) => TLK10232
(2) HS_side
    TLK10232 (1lane 10G-KR) => opt.SFP module => optic Cable => opt.SFP module => TLK10232 (1lane 10G-KR)

When our PCBs operate with this particular chip, we faced the following problem: after initialization and reaching normal operative mode , HS FEC Correctable Error sometimes appeared. (Reg Addr:0xAC、Dev Addr:0x01)
・Error occurrence frequency changes in every off/on.  For example, error occurs 10 times per minute and we power off/on PCBs , initialize normal operative setting ,then, error occurs 10 times per day.
・Error occurs in NOT ALL PCBs. Error occurs in some serial numbers.
・The Low speed side is always good.
・Length of traces from TLK10232 to SFP module is less than 20mm . (No vias or stubs)

We use this chip in 10GKR FEC Mode and following is initiation setting.
1. Reset device (assert RESET_N and PDTRXA_N pins)
2. Make sure the reference clock selection  – we use 156.25 MHz ,so no register changes.
3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
4. Disable link training by writing 16’h0000 to 0x01.0096
5. Write 16’h03FF to 0x1E.8020.
6. Write HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101.
7.    Write 16’h0003 to 0x01.00AB - Enable 10GBASE-R FEC
8. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.
9.    Clear Latched Registers (including 0x01.00AC)

We used information from the following :
e2e.ti.com/.../1833175
tlk10232_BringupProcedures_v2.pdf
tlk10232.pdf
4520.TLK10034_link_training_app_note (10).doc

★We don’t understand the cause of HS errors and why sometimes(some chips) error occurs and don't occurs . Please can you help us!

12 Replies

  • Hello,

    A support engineer has been assigned and you should be getting a response soon.

    Regards,
  • In reply to Jorge Llamas (SWAT):

    Hi,

    Thank you for your reply. We are waiting for support.

    Regards,
  • In reply to user499018372:

    Hello,

    Since this device is intended for backplane applications in “bringup procedures” are not specified how to link-up with optical modules despite this device supports interfacing with SFP+ optical modules. For XAUI-to-SFI/XFI operation, you will need to configure the device for 10GBASE-KR mode and disable the features specific to backplane Ethernet like Clause 73 auto-negotiation and 10G link training. To do this, follow this procedure:

    1. Reset device (write a 1 to 0x1E.0000 bit 15 or assert RESET_N pin)
    2. Make sure the reference clock selection (156.25 MHz or 312.5 MHz) is correct – this is done through register 0x1E.001D bit 12 (default is 156.25 MHz).
    3. Disable auto-negotiation by writing 1’b0 to 0x07.0000 bit 12
    4. Disable link training by writing 16’h0000 to 0x01.0096
    5. Write 16’h03FF to 0x1E.8020. This allows the link settings that would normally be configured through KR training to be configured manually instead.
    6. Depending on the link conditions, you may need to change the default configuration of 0x1E.0003 and 0x1E.0004. For optical connections, we typically recommend changing HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101. This can be a starting point, but you may need to do some BER testing to optimize the values.
    *** Enable FEC function through reg 0x01.00AB writing 0x0003
    7. Issue a data path reset by writing 1’b1 to 0x1E.000E bit 3.

    At this point the device should be properly configured.

    Once the procedure above is done, have you performed a BER testing trying different values for HS_SERDES_CONTROL_2 & HS_SERDES_CONTROL3?

    Focus first on:
    HS_ENTRACK
    HS_EQPRE
    HS_PEAK_DISABLE
    HS_H1CDRMODE

    Unfortunately, these stage of "tuning" is exhaustive since user needs to sweep different values in different combinations for HS_SERDES_CONTROL_2 & 3, this process is automatic when Link Training is enabled but in 10GBASE-R this feature must be disabled.

    Best Regards,
    Luis Omar Moran
    High Speed Interface
    SWAT Team
  • In reply to Luis Omar Moran:

    Hello,

    Thank you for your reply.

    As I showed above, I configure the device for 10GBASE-KR mode and disable the auto-negotiation and link training.
    But I don't perform tuning refister values for HS_SERDES_CONTROL. Only try recommended value. (HS_ENTRACK (0x1E.0004 bit 15) to 1’b1 and HS_EQPRE (0x1E.0004 bits 14:12) to 3’b101))
    So I will try tuning (testing BER) first focus on  HS_ENTRACK HS_EQPRE HS_PEAK_DISABLE HS_H1CDRMODE.

    However, tuning all of these registers takes so much time because error occurence frequency greatly differs by chips (error occurs in some chips and never occurs in others) and every device on/off.


    So, my Questions are following:
    1. Why error occurrence frequency GREATLY changes by chips and every device on/off? Is there any registers that can isolate cause of problem?

    2. Do you have some recommended value for tuning registers (HS_ENTRACK HS_EQPRE HS_PEAK_DISABLE HS_H1CDRMODE) if I input our PCB ArtWork condidion (tarce length, impedance control, material, PCB layout etc)

    Regards,

  • In reply to Luis Omar Moran:

    Hello,

    We tried tuning register focus on HS_ENTRACK,HS_EQPRE,HS_PEAK_DISABLE,HS_H1CDRMODE.

    However, HS fec error occurs in all register settings we tried.


    We tried following register setting and checked fec error count.
    (About 30min. after link-up, we dumped fec correctable error count reg.)

                                        setting A     setting B     setting C     setting D    setting E    setting F    setting G
    HS_ENTRACK             0x1           0x0              0x1              0x1            0x1            0x1            0x1
    HS_EQPRE                 0x101        0x001         0x101          0x110        0x101        0x110        0x101
    HS_CDRFMULT          0x01          0x01           0x01            0x01          0x01          0x1            0x10
    HS_CDRTHR              0x01          0x01           0x01            0x01          0x01          0x1             0x01
    HS_PEAK_DISABLE   0x0           0x0             0x1              0x1            0x1            0x0             0x0
    HS_H1CDRMODE      0x0           0x0              0x0              0x0            0x1            0x0            0x0
    HS_TWCRF                0x00000    0x00000     0x00000     0x00000     0x00000    0x00000    0x00000
    ------------------------------------------------------------------------------------------------------------------------------------------
    FEC error count          0xB           0x188          0x6             0x3             0x731        0x70          0x3


    Do you have some suggestion about register setting or other hint for HS error?

    Regards,

  • In reply to user499018372:

    Hi,

    Try the procedure without FEC function. Then try different values for the tuning, I know that this procedure is exhaustive. Could you send us the status of the next registers when you are performing the tuning?

    CHANNEL_STATUS_1

    HS_ERROR_COUNTER

    Thanks,

    Luis

  • In reply to Luis Omar Moran:

    Thank you for your reply,

    I performed PRBS mode and checked HS_ERROR_COUNTER using two TLK10232EVM boards.
    Then, HS error occured in one of them.

    I performed following initiation procedure for two boards after GUI opended.
    (0x07, 0x0000) 0x2000 write (Disable auto-negotiation)
    (0x01, 0x0096) 0x0000 write (Disable link training)
    (0x1E, 0x8020) 0x03FF write (VS_SERDES_CFG_OVERRIDE_CTRL)
    (0x1E, 0x0003) 0x5848 write (HS_SERDES_CONTROL_2)
    (0x1E, 0x0004) 0xD500 write (HS_SERDES_CONTROL_3)
    (0x1E, 0x000E) 0x0008 write (Issue a data path reset)
    (0x1E, 0x000B) 0x3F10 write (LOOPBACK_TP_CONTROL)
    (0x1E, 0x0010) read (HS_ERROR_COUNTER reg clear)

    Then, leave 12 hours and read CHANNEL_STATUS_1 and HS_ERROR_COUNTER.

                                                                CHANNEL_STATUS_1                HS_ERROR_COUNTER
    TLK10232EVM Board No.1      0x200(1st read)  0x1803(2nd read)                       0x0
    TLK10232EVM Board No.2      0x210(1st read)  0x1813(2nd read)                       0x7


    What is the difference between two boards and is it nessesarry tuning for TLK10232EVM Board?

    Regards,

  • In reply to user499018372:

    Hi,

    Could you try the next procedure?

    (0x07, 0x0000) 0x2000 write (Disable auto-negotiation)
    (0x01, 0x0096) 0x0000 write (Disable link training)
    (0x1E, 0x8020) 0x03FF write (VS_SERDES_CFG_OVERRIDE_CTRL)
    (0x1E, 0x0003) 0x5848 write (HS_SERDES_CONTROL_2)
    (0x1E, 0x0004) 0xD500 write (HS_SERDES_CONTROL_3)
    (0x1E, 0x000B) 0x3F10 write (LOOPBACK_TP_CONTROL)
    (0x1E, 0x000E) 0x0008 write (Issue a data path reset) //Data path reset is performed once the desired whole configuration is done
    (0x1E, 0x0010) read (HS_ERROR_COUNTER reg clear)

    Thanks,
    Luis
  • In reply to Luis Omar Moran:

    Hi,

    Thank you for your reply, I will try your procedure.

    By the way, is there any performance Test Report of HS Reciever?
    I found HS Trinsmitter performance reoport <www.ti.com/.../tidu347.pdf>
    However, I couldn't find HS Reciever test report.
    In SFF-8431, HS Recierver jitter tolerance (BER) specification is defined.(I send SFF-8431 and you will find jitter spec in page 32.)

    Additionnarry, I also couldn't find LS side (xaui) test report.


    Could you give me these testreports?

    Regards,

    Regards,SFF-8431.PDF

  • In reply to Luis Omar Moran:

    Hi,

    I tried your procedure.
    However, HS error has occured one of TLK10232EVM board again.
    I performed your procedure after GUI opened.Then, leave 12 hours and read CHANNEL_STATUS_1 and HS_ERROR_COUNTER.


                                                                CHANNEL_STATUS_1                HS_ERROR_COUNTER
    TLK10232EVM Board No.1      0x200(1st read)  0x1803(2nd read)                       0x0
    TLK10232EVM Board No.2      0x310(1st read)  0x1803(2nd read)                       0x2

    Is there anything wrong with my procedure or setup, and could you give me HS reciever test reports?

    Regards,

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