On the ISO5852SEVM, what’s limiting the Vdc to go over 500V? Is it the TO-220 package through holes?
Can you please share the layout of the board in PDF?
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On the ISO5852SEVM, what’s limiting the Vdc to go over 500V? Is it the TO-220 package through holes?
Can you please share the layout of the board in PDF?
Hey David,
Great to hear from you!
Where did you see the 500V warning? The board says 50V max on it.
I’ll see if I can find the layout in pdf for you.
Hi David,
The 50V limit is set by the clearance of PCB traces.
With regards,
Xiong
Hi David,
I couldn't find the pdfs, but here are the Gerbers which should be better anyway.
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