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TLK10232: general purpose mode

Part Number: TLK10232
Other Parts Discussed in Thread: DS125DF1610

Does TLK10232 can run at 1.25G general purpose mode. I need it to bypass all 1000-x signal. does it OK?

Thanks

  • Hello,

    TLK10232 can be used in general purpose mode (see section 5 of the datasheet). Section 5.8 specifies the rates supported for general purpose mode, which include 1.25Gbps.

    Regards,
    Yaser
  • I use it with reference clock 312.5Mhz.

    MPY=8 both HS and LS

    LS Q rate  HS Eight rate

    01 -->3402  

    I connect it to DS125DF1610, it will have error. when it use at KR mode, it is OK. But, I need it as repeater only. 

    my design 

      sfp --> ds125df160 --> tlk10232 --> 1G phy.

  • when I work at general purpose mode 1.25G with 312.5Mhz, reg 0x10 = 0 and reg 0x0f = 0x1E1B.

     does it need to care bit "4"?

    7    TX_FIFO_UNDERFLOW Not applicable in 1GKX mode. When high, indicates underflow has occurred in RO/LH
         (RG) the transmit datapath (CTC) FIFO.
    6     TX_FIFO_OVERFLOW When high, in 10GKR and 10G modes indicates overflow has occurred in the RO/LH
          (RXG) transmit datapath (CTC) FIFO.
    5    RX_FIFO_UNDERFLOW Not applicable in 1GKX mode. When high, indicates underflow has occurred in RO/LH
          (RG) the receive datapath (CTC) FIFO.
    4   RX_FIFO_OVERFLOW In 10GKR and 10G modes, high indicates overflow has occurred in the receive RO/LH
         (RXG) datapath (CTC) FIFO. In 1G-KX mode, high indicates a FIFO error.

  • Hi sir,
    I setup below for 1.25G
    1d =0x3000 clk 312.5
    02 = 8115 enable pll x8
    03 = ab4f rx, tx 8 rate
    01 =3402 1:1, general mode, ref=1
    06 =f114 x8
    07 = 5e06 4 rate enable serdes

    regiter 0x0f =1f1b 0x010 = 0xffff
    it seem have problem. Do I need setup others register for 1:1 mode?
  • Hi Cannie,

    Could you try the next procedure?

    General Purpose Mode 1:1

    REFCLK: 153.6/122.88MHz

    1. Ensure ST input pin is Low.

    2. Ensure MODE_SEL input pin is High.

    3. Ensure PRBSEN input pin is Low.

    4. Ensure REFCLK_SEL pin is Low.

    5. Reset device (Issue a hard reset or soft reset, RESET_N asserted for at least 10us or write 1b'1 to 30.0.15

    6. Write 4'b1011/1101 to 30.2.3:0 to set HS_PLL_MULt multiplier to 16/20x

    7. Write 2'b01 to 30.3.9:8 to set HS_RATE_TX to Eight Rate.

    8. Write 3'b101 to 30.3.2:0 to set HS_RATE_RX to Eight Rate.

    9. Write 2'b11 to 30.1.13:12 to set mode 1:1

    10. Write 2'b01 to 30.7.9:8 to set LS TX SerDes lane rate to Half Rate.

    11. Write 2'b01 to 30.7.1:0 to set LS RX SerDes lane rate to Half Rate.

    12. Issue a data path reset. Write 1'b1 to 30.14.3

    13. Wait for 1000ms.

    Please try the procedure above and let us know your results.

    Best Regards,

    Luis Omar Moran

    High Speed Interface

    SWAT Team