• State TI Thinks Resolved
  • Locked Locked
  • Replies 1 reply
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 510 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN65HVD11: Voltages of INTERNAL vs External Failsafe Biasing

Gerhard van Rensburg
Intellectual 400 points
Part Number: SN65HVD11

The newer RS-485 devices claim to have built in failsafe circuitry.

So if NO external biasing resistors are used, what is the voltage on the A/B lines.

On the other hand, if the master has say 1K Pull-up/down for bias, and 120 Ohm for Termination, then in a 3V3 system, the idle voltages will only be 187mV apart.

This is less than the 200mV some of the information suggests is the minimum.

So unless the External bias resistors are around 750 Ohm to 820 Ohm, with a 120 Ohm Termination, the Vid is too small for reliable communication?

Then that all goes out the window if the Master has 120 Ohm termination, with 500 Ohm Biasing, and the Slave (receiver) has 120 Ohm Termination

This gives a 187mV idle state for Vid (Va - Vb), which is lower than the recommended 200mV?

I guess the

VIT+ Positive-going input threshold voltage of -65mV
and
VIT– Negative-going input threshold voltage of -200mV is a little unclear.

Any help appreciated

  • 0
    TI__Guru 62910 points
    Hello Gerhard,

    For more details on calculating failsafe bias resistances, you may want to reference this application note: www.ti.com/.../slyt324.pdf. You're right that ensuring a minimum of 200 mV differential with a 3.3-V rail and effective termination resistance of 60 Ohms can result in some fairly "strong" biasing resistances. Using transceivers with internal failsafe biasing or with receiver thresholds that are more sensitive than the worst-case +/-200 mV required by TIA/EIA-485 can help in this case.

    For our transceivers that implement internal failsafe biasing, an offset is generally not observed on the A/B bus pins (assuming external failsafe biasing is not implemented). I say "generally" because I have seen some exceptions with one or two much older devices (of which HVD11 is not included). This means that the biasing implemented in one transceiver will not carry forward to the other transceivers populated on the bus. One other thing to note is that it is OK to implement external failsafe biasing with transceivers implementing internal biasing - there will not be conflict between the two.

    Regards,
    Max