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Input transition rise or fall rate

Hello,

I'm trying to understand this:

if rise/fall time is tr=freq/3 (as a rule of thumb), I have Vcc=3.3 so the rate is 10 nS/V.

As I understand it the minimum input frequency is 1/30nS = 33.3 MHz

Do I understand it correctly?

Thank you

Hanan

4 Replies

  • Hi Hanan,

    I do not quite understand what you are trying to ask. Can you providem ore details about your design and if you are looking at a particular TI part regarding this question?

    Usually the rise/fall time limits the maximum possible input frequency, since a non-zero transition time implies that, at the maximum allowable frequency, the incoming signal will no longer switch fast enough to meet the voltage threshold requirements for high-to-low and low-to-high transitions. I am not aware of a similar requirement for minimum input frequency. In several TI parts that use a reference clock, the minimum input frequency is limited by an internal PLL that may lock to the reference clock.

    Thanks,

    Michael

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  • In reply to Michael Lu (Santa Clara):

    Hi,


    I'm referring to "www.ti.com/lit/an/szza036b/szza036b.pdf " page 35 where you can read  that TI explains that "dT/dV" defines slow changes and not fast change, so it imply (in my opinion)  to the minimum frequency.

    Am i correct?

    Hanan

  • In reply to Hanan Zeltzer:

    Hi Hanan,

    I read through the section of the document you referred to as well as the follow-up additional document (SCBA004), specifically geared towards slow rise/fall times for CMOS:

    I agree that slow edges can be a problem, since especially slow edge rates can cause excessive output errors or oscillations due to voltage transients on the device's power system.

    However, the issue of slow edges does not necessarily correspond to a minimum frequency limit.

    On one side, slow edges is a problem for limiting the maximum frequency, since you cannot operate at a frequency that requires "1010" bit transitions that would switch significantly faster than the signal can transition from low-to-high. On the other side, you should not have an issue with minimum operating frequency so long as your rise and fall time transitions are met. For example, even if you operated at 1 Hz, if the high-to-low and low-to-high transitions still occur within 10 ns/V for an LVT logic part, then you can still operate at this minimum frequency without issue.

    Therefore, I would associate the rise/fall time requirement as a factor that corresponds to compatibility between Tx and Rx rather than minimum operating frequency so that there are no issues with the edge rate during data transmission.

    Thanks,

    Michael

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  • In reply to Michael Lu (Santa Clara):

    Hi Michael
    I'm also interesting about "input transition rise or fall rate" above you posted figure3. For AHC series, the max input transition rate is 20 ns/V.
    Does it means the input transition rate of we designed should faster than spec defined? Such like 10n/V? Or 30 ns/V is acceptable?