TUSB1310A: TUSB1310A/FPGA Rx Loopback State Returns Multiple Bit Errors When Receiving Single Bit Errors

For USB3 Rx jitter tolerance testing, the LTSSM Rx Loopback state is used. It was observed during Rx jitter tolerance testing that during very low bit-error-rates (1x10e-12 to 2x10e-12), the LeCroy PeRT3 tolerance tester detects bit errors in clusters most of the time and rarely as single bit errors. The USB3 Rx jitter tolerance test allows for 1 bit error max to pass a giving SJ frequency. This behavior was suspicious and so was investigated using forced single-bit-error insertion function of the PeRT3. With additive jitter sources turned off (RJ/SJ), PeRT3 forced single-bit-errors resulted in loop backed data with either 1, 2, 3, or 4 bits at a time, but the majority of time as 2, 3, or 4 bit errors. With forced single-bit-error insertion, when TUSB1310A/FPGA registers a disparity error, a single bit error is looped back to PeRT3. With forced single-bit-error insertion, when TUSB1310A/FPGA registers an 8B/10B decoder error, 2, 3, or 4 bit errors are looped back to PeRT3. The Cypress CY4603 hub and TI TUSB8040A hub always return single bit errors for a PeRT3 forced single-bit-error.

This behavior was investigated and it was determined that this behavior is an outcome of the external loopback workaround required by TI due to a bug with the TUSB1310A internal loopback:

TUSB1310A Errata (sllz063.pdf, SLLZ063–January 2011):

"Problem: Corrupted SKIPS returned to USB3 Loopback Master.Work Around: Implement external loopback in FPGA.

Severity: Low"

However, according to the USB3 spec, the Receiver Loopback must be implemented in the 10b domain:

USB3 Spec (USB_3_1_r1.0.pdf):

 “6.8.4 Receiver Loopback

The entry and exit process for receiver loopback is described in Chapter 7.

Receiver loopback must be retimed.  Direct connection from the Rx amplifier to the transmitter is not allowed for loopback mode.  The receiver shall continue to process SKPs as appropriate.  SKP symbols shall be consumed or inserted as required for proper clock tolerance compensation.  Over runs or under runs of the clock tolerance buffers will reset the buffers to the neutral position.

During loopback the receiver shall process the Bit Error Rate Test (BERT) commands. Loopback shall occur in the 10-bit domain for Gen 1 operation and in the 132-bit domain for Gen 2 operation.  No error correction is allowed.  All symbols shall be transmitted as received with the exception of SKP and BERT commands.”

So, due to TUSB1310A bug and required workaround it is implemented in the 8b domain in the FPGA which results in single bit errors in the 10b domain being converted into either single-bit-errors or multi-bit errors in 8b domain due to TUSB1310A 10b to 8b code conversion:

“5.3.5.3 8b/10b Decode Errors

When the TUSB1310A device detects an 8b/10b decode error, it asserts a SUB symbol in the data on the RX_DATA where the bad byte occurred. In the same clock cycle that the SUB symbol is asserted on the RX_DATA, the 8b/10b decode error code (100b) is asserted on the RX_STATUS. An 8b/10b decoding error has priority over all other receiver error codes and could mask out a disparity error occurring on the other byte of data being clocked onto the RX_DATA with the SUB symbol.”