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TXS0108E: B side Low level problems.

Part Number: TXS0108E

hi.

I use to TSX0108E level Shifter.

VCCA = 3.3V  A side connected for FPGA.

VCCB = 5V B side connected for some communication chip.(i can't tell you the name of chip. sorry)

the problem is coming from B side.

B side connected signal  state default is High. it is a Clk signal 4.8kHz.

I want this signal to operate from 5 v to 0 v, operating at 5 v to 2.5v.

Sometimes, at the beginning of the low descent, it behaves like 0v, but again, it behaves as if it were 2.5v.

like this.

What I suspect is the falling time of the signal.The falling time is approximately 250 ns.

The current phenomenon is solved by using the 51k Pull-Down Resistance, but I wonder if it is reliable.

5 Replies

  • Hi Ian,

    I have notified the appropriate applications engineer - he will be back with you soon.


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  • 2.5 V is not a valid logic level.

    Please show the schematic. What is the actual problem you're trying to solve?
  • In reply to Clemens Ladisch:

    i know 2.5V is not valid logic level.

     

    CLK is 1.2 kHz. this clk pin output level 5V high, 0V Low. but remove the R1(51k) signal is like this.

    how to solve this without 51k pull down???

    If the cause of this problem is  falling time , do I need to add a 51k pull-down resistor?

  • In reply to Ian Yun:

    This might indicate that the FPGA does not have enough drive strength to pull low the entire line through the TXS's internal pull-up resistors. (See sections 8.3.2 and 8.3.3 of the datasheet.)
    How is its clock output driver configured?
  • In reply to Clemens Ladisch:

    clock is just sync signal for synchronous serial communication. so..slow falling time got a no problems?
    i will check a FPGA I/O pin setting....if you have advice for FPGA I/O setting?(VHDL)

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