This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SN74AVC32T245 - What is the max skew between the outputs

Hi Support Team

Can you provide us with the maximum skew between the outputs?

Thanks

Jeff Coletti

  • Hello Jeff,

    Can you clarify what you mean by skew? Are you referring to the propagation delay between the input and the output?
  • Hi
    If I put the same signal into each input, what will the max difference be in output times from the fasted channel to the slowest channel, so for example if channel 1(slowest) in the device has a prop delay of 3.3nsec, and channel 2 (fastest) has a prop delay of 2.7nsec then the skew is 0.6nsec. Typically this is a clock measurement where we send a signal into a fan out buffer, but it is also important on a bus.

    Cheers
    Jeff
  • This is not spec'd on the data sheet but when can infer the worst case skew using the Switching Characteristics tables. For example, for Vcca = 1.5V and Vccb = 3.3V with direction A -> B the minimum propagation delay is 0.5ns and the maximum propagation delay is 3.7ns. By subtracting the minimum value from the maximum value we can assume that the worst case skew between any two inputs at these voltages will be 3.2ns.

  • please refer to this e2e post on channel to channel skew :
    e2e.ti.com/.../394126

    The logic devices guarantee 1ns skew into equal loads, typ will be 250ps. With many bits switching simultaneously the skew can vary .