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TXS0104E: TXS0104 Question

Jim CHEN
Expert 4795 points
Part Number: TXS0104E

Hi Team,

I have one question about TXS0104E and need your quick support.

When TXS0104E A side signal has been PU to High, but B side signal still keep Low，and then TXS0104E is turned on, whether A signal will be shortly pull low (not to 0V) for a few (ms)time, then back to High again ?

Please refer to below waveform we measured , if unmount TXS0104E , then won’t see the NRST step rising delay.      Please help to give me some comments, thank you. 

  • 0
    TI__Guru* 96591 points
    Hi Jim,

    I don't completely understand your question. Let's see if I can clarify.

    Is the +3V0 line one of the supply voltages for the TXS0104E?

    Is the other supply line for the TXS0104E constant during this process?

    I can't see the time scale or voltage for the scope plot shown -- I assume this is in ~ms scale and 1V/div for the blue line (ch 2) and 2V/div for the yellow and pink lines (so that means you are translating 1.8V to 3.3V?).

    Your desired output is to have the blue line drive low as soon as +3V0 goes high, and then a few milliseconds later, go high again. Is this accurate?
  • 0
    TI__Mastermind 23925 points

    Hello Jim,

    When you turn it on, there are two possible scenarios:

    1, The B side will dominate, and will pull and hold the A side low until the B side drives high again.

    2. The A side will dominate, and the B side will be pulled high.

    Do you have any external pull-ups, or is A being pulled up through the internal 10k? I am assuming you will be pulling B side low through a CMOS driver. Is this correct?

  • 0 in reply to aozer
    Guru 11785 points

    Hi Sirs,

    Please allow me to update this question.

    1. Purple line is A side input signal.

    2. Yellow line is VCCB

    3. Blue line is B side output signal

    For now, After A side already power on then we turn on IC.

    We found B side will effect A side to drop around 1v voltage, after 2 ms then A side will keep high.

    We don't know why?

    Is possible because B side loading is too heavy on turn on?

    Could you help us to clear this issue?

    Thanks for your reply.

     

  • 0 in reply to Shu-Cheng LIN
    TI__Mastermind 23925 points
    Hello,

    Do you have OE enabled or disable when this occurs?
  • 0 in reply to aozer
    Guru 11785 points

    Hi Aozer

    Thanks for your reply.

    On this occurs. the OE is high and same as VCCA.
    The power sequence is VCCA and OE already high, then we turn on the VCCB.
    So we found there had drop voltage(around 1v) on A side when we turn on the VCCB, After 2ms then A side voltage will be normal.
    Could you help explain this phenomenon?? is normally or?
    By the way, our power sequence have any risk?

  • 0 in reply to Shu-Cheng LIN
    TI__Mastermind 23925 points

    Hello,

    There is no risk of damage with your power sequence. However, when you power on with OE enabled there is a chance that a glitch can occur at the output. Would it be possible to keep OE at ground when powering on VCCB?

    Do you have any external pull-ups? If so, what are the values? Approximately how long is the delay between when VCCA and VCCB ramp up? I can try to replicate your setup in the lab and see if the same thing occurs for me. 

  • 0 in reply to aozer
    Guru 11785 points

    Hi Aozer,

    Many thanks for your reply,

     We can’t keep OE pin LOW when BIOS finished GPIO initialization.

     OE should turn to HIGH when system entering S0 state, so that it can initialize the Finger Print device immediately, otherwise, this function should be failed.

     Our solution is change Seq of A/B side signal power on timing. For now, the B side signal (NRST) will go to HIGH earlier than A side (MCU_RST), and the step waveform is gone.

     But  we still need to confirm if any possible that step waveform is caused by the wrong power on timing between A/B side , just like you say before

    " The B side will dominate, and will pull and hold the A side low until the B side drives high again." 

  • 0 in reply to Shu-Cheng LIN
    Guru 11785 points

    Hi Aozer,

       Update state.

    There is no external PU/PD on both sides of  TXS0104E with the two signals.  And VCCA will power on when AC plug in or system is out from G3 mode, and  VCCB , by original design, it depends on user’s option, normally, it will power on after BIOS finished  GPIO initialization, the delay time is less than 400ms.

    Thanks.

  • 0 in reply to Shu-Cheng LIN
    Guru 11785 points

    Hi Aozer,

    Sorry for pushed.

    Could you provide your suggestion for us?

    Thanks!!

  • 0 in reply to Shu-Cheng LIN
    TI__Guru 56100 points
    Hi Shu-Cheng,

    My suggestion is to have I/Os grounded while have Vcca and Vccb ramp simultaneously or Vcca leading Vccb is fine.
    with I/Os floating , it could have minor glitches but not serious which could cause malfunction.
    please let us know what you find out in your case.
  • 0 in reply to ShreyasRao
    Guru 11785 points

    Hi ShreyasRao,

    Thanks for your reply, the last confirm one thing.

    The step waveform is caused by the wrong power timing between A/B side, right?

    Thanks!!