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Part Number: TXS0108E
I use to TSX0108E level Shifter.
VCCA = 3.3V A side connected for FPGA.
VCCB = 5V B side connected for some communication chip.(i can't tell you the name of chip. sorry)
the problem is coming from B side.
B side connected signal state default is High. it is a Clk signal 4.8kHz.
I want this signal to operate from 5 v to 0 v, operating at 5 v to 2.5v.
Sometimes, at the beginning of the low descent, it behaves like 0v, but again, it behaves as if it were 2.5v.
What I suspect is the falling time of the signal.The falling time is approximately 250 ns.
The current phenomenon is solved by using the 51k Pull-Down Resistance, but I wonder if it is reliable.
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In reply to Clemens Ladisch:
i know 2.5V is not valid logic level.
CLK is 1.2 kHz. this clk pin output level 5V high, 0V Low. but remove the R1(51k) signal is like this.
how to solve this without 51k pull down???
If the cause of this problem is falling time , do I need to add a 51k pull-down resistor?
In reply to Ian Yun:
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