Hello,
we have to guarantee, that there are no bus contention issues between memory and SN74ALVC164245.
What if it would be guaranteed to set DIR pin correctly, before we activate the level shifter via EN (approx. >=1ns setup time)? And for the disable, at first we deactivate the level shifter and afterwards set the direction back (approx. >=1ns hold time).
According to datasheet for such sequence the level shifter should change from "isolation state" to "B to A operation".
Is it guaranteed, that with this sequence the level shifter doesn't drives the wrong direction ("A to B operation") at no time?
Or could the case happen, that DIR pin sets the direction slower than the EN pin activates the shifter? If this could happen, which setup/hold time is needed to avoid contention issues?
Thanks & Regards
Martin