SN74LVC16T245: SN74LVC16T245ZQLR time delay

Nir Flysher

Part Number: SN74LVC16T245

Dear Team,

Could you please advise regarding my customer question below ?

I am trying to figure out the delay time DIR to A or B according to the formulas in para 10.1.1 of the data sheet.

Unfortunately the data for delay for DIR to A or DIR to B (tplh) is not presented in the data sheet.

Regards,

Nir.

over 6 years ago

0 Emrys Maier over 6 years ago

TI__Guru* 96591 points

Hi Nir,
The propagation delay for DIR to A or B is equal to the delay from OE to A or B. Note that the propagation path is equivalent in the logic diagram from page 1 of the datasheet.

0 Nir Flysher over 6 years ago in reply to Emrys Maier

TI__Expert 3186 points

Dear Emrys,

Please see additional question from the customer regarding this :

The CPU data bus (and peripherals) connected to the B side (5v), and the A side (3.3v) connected to a FPGA. We have PU resistors in the A side.
We are not sure regarding the state of the OE during DIR change (CPU bus changed from write to the FPGA to read from FPGA and vice versa).
Please advice (in both case, A->B and B->A) if the OE should be at "1" during DIR change or is it enough to float the FPGA signals ?

BR,
Nir

0 Michael J Schultis over 6 years ago in reply to Nir Flysher

TI__Mastermind 24485 points

Hello Nir,

When switching directions, it is recommended to disable the outputs first, switch the direction, and enable the outputs.
In general you want to make sure that you don't have bus contention when switching the direction and you don't want to leave floating inputs as this could cause excessive current consumption. Floating inputs when the device is disabled can also cause excessive ICC as there is still an input structure with an undefined input voltage.

Best,
Michael

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SN74LVC16T245: SN74LVC16T245ZQLR time delay