Other Parts Discussed in Thread: SN74LVC1G07
I have two chips which communicate with each other using 1.8v CMOS I/O (1Mbs UART). One chip is on the normal 0v ground plane, but the second chip's ground is at .7v (so its I/O operates at 2.5v for high and .7v for low with reference to first chip's 0v ground), and this is part of the design so can not be changed.
Im trying to figure out the best way to translate these logic levels so I/O works correctly between them. One option is to just connect them with no level shifting, in which case the the first chip would be seeing 2.5v instead of 1.8v for high (it should be able to tolerate), and .7v for low instead of 0v (which would probably not be reliable for 1.8v low logic which is around .45v to be safe).
Other option is to use something like TXS0102, with its ground referenced to 0v, Vcca=1.8v and Vccb = 2.5v. Two questions with this, the low .7v signal from Chip 2 will be fed to the input of the TXS0102, but will this be low enough to trigger a 0v output for chip 1? Second when chip 1 is sending a low signal to Chip 2, since it will be driven down to 0v, chip 2 will see that as -.7v. Will this cause issues with the logic gate over time if its logic gate keeps seeing negative voltage for low?
I guess the main issue is how to properly shift the low level logic, since the TXS0102 will properly take care of the high logic in the upstream and downstream directions. I guess I would need some sort of logic gate that would "catch" a certain voltage range like chip 2's .7-1.15 low logic range, and force a 0v switch for the second chip but this sounds messy. What would solve this is if there was a chip that has separate ground pins for channel A/B.
Am I overcomplicating this an is there a simpler way to do this with voltage dividers for slow 1Mbs logic?
