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ISO3088: Termination resistor for half duplex mode

Part Number: ISO3088

I am planning to use ISO3088 isolation transceiver in a half duplex design. The reference design does not show any termination resistors. between the A and B pair. The device datasheet woth the IO diagram shows an Open Collector configuration, so how does the signal get driven?

Regards,

Amit Ashara

  • Hi Amit,

    Thanks for bringing this to our notice, yes the application report referred do not talk about termination resistor. Let me check on this.

    To answer your question, RS-485 network with ISO3088 also requires termination resistor at the longest end of the cable. The cable end has to be  terminated with a termination resistor, R(T) whose value matches the characteristic impedance, Z0, of the cable.

    Regards

    Tejas 

  • In reply to Tejas Hommaradi:

    Hello Tejas

    Thanks for clarifying the same. Since the output is Open Collector, how is the output being driven high?

    Also as per the Application note www.ti.com/.../snla049b.pdf ; between parallel termination and parallel termination + bias resistor, which one will you suggest is the most appropriate termination for ISO3088.

    In either cases, does the series resistor need to be before or after the termination; my guess is after the termination to avoid a voltage divider.

    Regards,

    Amit Ashara

  • In reply to Amit Ashara:

    Hi Amit,

    The RS-485 differential driver is implemented as an H-bridge output stage that drives current from terminal A to terminal B and vice versa, depending on the logic state at the data input D.

    As ISO3088 has internal fail safe biasing , Just parallel termination on external bus will be sufficient.

    Regards
    Tejas
  • In reply to Tejas Hommaradi:

    Hello Tejas

    Thanks for the confirmation.

    Regards,

    Amit Ashara

  • In reply to Tejas Hommaradi:

    Hello Tejas

    Since the ISO3088 has internal fail safe biasing, will the biasing be reflected on the A-B pair? I am asking the question as other devices on the bus may not have the fail safe biasing so want to make sure that I have fail safe biasing for the bus.

    Regards,

    Amit Ashara

  • In reply to Amit Ashara:

    Hi Amit,

    Sorry for the delay in response.

    The fail safe biasing is at input of the receiver, this causes output of the receiver to be high when the transceiver is disconnected from the bus (open-circuit), the bus lines are shorted (short-circuit), or the bus is not actively driven (idle bus).
    As the fail safe bias is on the input of the receiver, the biasing will not reflect on A-B Pin.
    Hence you may have to go with fail safe termination of the bus if other nodes on the bus do not have internal fail safe biasing.

    Regards
    Tejas
  • In reply to Tejas Hommaradi:

    Hello Tejas

    Thanks for responding. I do not understand one thing. If the fail safe biasing is on the input of the receiver and the pin is connected to the external IO pad, then why will the state not reflect on the bus. Is there a diode on the path that prevents the state from reflecting on the IO pad and thereby on the bus?

    Regards,

    Amit Ashara

  • In reply to Amit Ashara:

    Hi Amit,

    The fail safe biasing is at the input of the receiver of side 1 (logic side) and not on the BUS side. Hence this fail safe biasing will not reflect on the BUS.

    This fails safe bias ensures that the receiver output is high when ever the BUS is not actively driven and is not the fail safe termination of the BUS.

    Regards

    Tejas