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Part Number: ISO7220A
I'm seeing an issue with this device which produces a pulse at B1 and B2 when the device is powered. Without any input to A1 or A2.
Checking the way the device is powered at switch on, it appears that if V1 and V2 are not applied at the same time, then a large spike is generated from B1 and B2.
This is not highlighted in the device data. These large spikes are controlling the gates of 32A mosfets which are failing possibly because of this issue.
It looks like i'm going to have to syncronise the power application of V1 and V2 to this device to avoid the issue.
Has anyone at TI seen this issue or know of a simple method to eradicate the problem?
The output of the device goes to the failsafe state till the input side is powered on and the input signal is detected. Since the default state of 7720A is HIGH, you would see VCC2 at the outputs for a short time.
This can be solved by using an 'F' part like the ISO7320F which will have the failsafe state set to LOW.
If you are looking for reinforced isolation in your system ISO7720F will be suitable for your application.
In reply to Anand Reghunathan:
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