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ISO7841: Input signal on OUT pin

Part Number: ISO7841

Hi Team,

We input high signal on OUT pin, and find the signal is pulled to GND. Is it normal symptom?

Are there any internal pull down circuit in ISO7841?


  • Hi Daniel,

    The OUT pin will reflect the data that is given to the IN pin. If the IN pin is given a LOW the OUT pin will also be a LOW (pulled to GND).
    What is the state of the corresponding IN pin when the signal at OUT is being applied?

    Could you also give some clarity as to why an input signal is applied to the OUT pin? Is this to test some specific system scenario?

    Anand Reghunathan
  • In reply to Anand Reghunathan:

    This can happen is ISO7841 (or ISOW7841) is used to isolate an SPI device. The isolated device (VCC2 side) only drives the isolated MISO signal when enabled by the chip select signal. Unfortunately, the ISO7841 drives the MISO signal on the VCC1 side, even if MISO on the VCC2 side is not driven by the device. This prevents other SPI devices on the VCC1 side using MISO.

    This can be overcome with a three-state buffer (1G125 for example) which allows SPI devices on the VCC1 side to use MISO when the isolated device is not enabled. It would be connected like this....