This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

  • TI Thinks Resolved

ISO7741: When ISO7741, isolation failure, what is the state of IO?

Part Number: ISO7741

Hi all
I want to know that after the ISO7741 isolation failure, is the IC IO output disconnected or short circuited? What is the detailed principle.
I have seen the ADI brand ADuM261N, ADuM262N, their magnetic isolating chip failure model is open.

  • Hi Ming,

    The failure mode will always depend on the type of stress applied to the device and ADI will also be similar to TI in this aspect.

    Please refer to Understanding Failure Modes. This whitepaper explains in detail the phenomenon behind the cause of failure open in TI isolators and also discusses in detail the different failure modes that can occur at a system level and how they can be avoided.

    Hope this helps answer your questions. Let me know if this is sufficient or if any additional data is required.
    Thanks.

    Regards,
    Anand Reghunathan

  • In reply to Anand Reghunathan:

    Hi anand
    Click the link page,I cann't find “Understanding Failure Modes ” contents. the page you've requested no longer exists.
  • In reply to Anand Reghunathan:

    Hi Anand
    click the link page, I cann't find " Understanding Failure Modes." contents, the page you've requested no longer exists.
    I want to know the detailed principle that What the failure model is?
  • In reply to Ming:

    Hi Ming,

    I'm not sure why the link didn't work. I'll paste it here again.
    www.ti.com/.../slyy081.pdf
    If the link doesn't work, the whitepaper can be found by searching "slyy081" or "Understanding Failure Modes in Isolators

    Please also take a look at the E2E blog (link below) which gives a summary of the whitepaper
    e2e.ti.com/.../understanding-isolator-failure-modes-for-safe-isolation

    These documents should be able to answer your query. If you still have doubts, please feel free to reply to this post and I would be happy to clarify.
    Thanks.

    Regards,
    Anand Reghunathan
  • In reply to Anand Reghunathan:

    Hi Anand
    I've read the document, “www.ti.com/.../slyy081.pdf”.
    the document mentioned that Failure mode 1: High voltage across the isolation barrier;Failure mode 1 will lead to isolators “fail short.”
    What is the meaning of “fail short.”? It means a short circuit between sides 1 and 2,No electrical isolation features?
    But ADI their magnetic isolating chip failure model seem be open.
  • In reply to Ming:

    Hi Ming,

    Apologies for the delay in coming back to you on your question.
    Thanks for going through the white paper titled "Understanding Failure Modes in Isolators". As you understood already, there are two failure modes that are being discussed in the article.

    Failure Mode 1:
    As explained and described in Figure 3 of the referred article, please note that most electronic device when exposed to stress levels more than what they are capable of then they get damaged catastrophically. When there is such damage on electronic components, the damage could lead to a complete failure or a partial failure and it can never be determined if the failure will result into a complete short or with some resistance. Since there is a chance that it can fail short at least once in few tens or hundreds of samples, it safe to assume that most electronic components fail short when exposed to excessive stress levels.
    e.g., consider applying higher voltage to VCC pin of any digital isolator (TI or competition) and apply higher voltage than the maximum voltage the device can withstand, let's say 10V. When you test the device for this, some devices can fail completely short and some might fail with some impedance.
    Since TI's reinforced digital isolators have one of industries highest isolation ratings, it is very unlikely for TI device to get damaged than other lower isolation rated devices.

    Failure Mode 2:
    As described in Figure 5 of the article, TI's reinforced digital isolators have two two series caps (hence two barriers). When there is a damage on one die, the isolation cap on the other die stays intact maintaining isolation across the barrier. Please note that this is not the case with single isolation barrier devices. A damage on one die could lead to damage of the single isolation barrier.

    I hope that answers your question, let me know if something is not clear to you. Thank you.


    Regards,
    Koteshwar Rao

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.