• Resolved

ISO7731-Q1: Output State in transition from PU to PD at Vcco

Part Number: ISO7731-Q1


My customer have some question about output state in transition from PU to PD at vcco for ISO77xx family.


I show their block diagram and the timing chart that they are concerned as follows.

<Use Case>

Vcci in ISO77xx is the same power rail as MCU.

Vcco in ISO77xx is the different power rail as LIN Transceiver.

Vcci = PU

ENx = Open

INx = High

Vcco = PU -> PD -> PU

In this case, they want to keep high on the OUTx.

<My understanding>

Zone 1 : OUTx = High (However, the OUTx high level depend on Vcco voltage.)

Zone 2 : ??? (I think it is not made Low state and High-Z state.)

Zone 3 : OUTx = High (However, the OUTx high level depend on Vcco voltage.)


Is "Undetermined" listed in D/S (SLLSEU3A) P.20 Table 2 the meaning as "Undefined" ? 


In what kind of state will the OUTx be in Zone 2 ?


Is there a way to maintain the OUTx in the state of High in Zone 2 ?

(I accept that it depend on Vcco voltage.)

Best Regards,

Hiroshi Katsunaga

  • Hi Hiroshi-san,

    Thank you for posting all the necessary details regarding your query, please find below my response to your questions.

    Yes, when VCCO is PD the output is in "Undetermined" / "Undefined" state.

    In Zone 2, VCCO is going to be less than 1.7V. For VCCO<1.7V, the output will be in high impedance. Please note that the parasitic capacitance on output pin may take a small amount of time to discharge fully based on the load connected.

    Like you have mentioned, without VCCO or any other power supply available at output it would not be possible to hold the pin HIGH.

    Thanks & Regards,
    Koteshwar Rao
  • In reply to Koteshwar Rao:

    Hi Koteshwar-san,

    Thank you for your fast response and your clear comments.

    I understood your all comments.

    Thank you for your cooperation !

    Best Regards,
    Hiroshi Katsunaga