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ISO1540: ISO1540 Side2 to Side1 limitation

Part Number: ISO1540


We have a FAN controller on side 1 and a FAN on side 2. We are experience an issue that “when Side B FAN is not connected the are experience clamping on side 1 to ~1 to 1.2V”. In other words, side A is limited to 0V and 1.2V levels. The pullup resistor for SDA2 is built into the fan so my suspicion is that the side 2 is settling to a voltage below the side 2 low threshold and that a low is being passed to side 1 when the fan is disconnected. However, if this were the case then side 1 should be “clamping” at 650mV to 800mV.


Looking at the specs of an analogous pin-to-pin part from another vendor, there spec implies that Side 1 voltage is limited to less than what side 2 voltage is. Is this true for a TI device. In other words, If SDA2 is sitting at 2V, would SDA1 be limited to 2V as well? I doubt this is the case, but please confirm.


Also, what may help me further debug this is a easier to understand explanation of Figure 26 in the ISO1540 datasheet. Specifically the right-side image (also pasted below). I’m confused as to what is causing Vol1 in the image. Please elaborate.


Thank you

  • Hey Cassidy,

    Thanks for using E2E. This is Abhi  (from the ISO apps team) following up on Dan's email response on this.  While we wait for our Apps expert for this part to respond to the first set of questions (likely on Monday), we thought we'll try to clarify the second part of your question (regarding Fig.26)  to help in the debug.

    To try and make Figure 26 easier to understand, I have put it next to Figure 25 as well as put section 8.4.2 below it. I've also reformatted this section and added some extra comments (purple font) and highlights. The key to the extra step in the SDA1 waveform on Fig 26(right side) is because it is not immediately noticeable since it is being actively overwritten by the master driving a low on the same pin externally at the same time (higher strength).


    8.4.2 Transmit Direction (Right Diagram of Figure 26)

    • When a master drives SDA1 low, SDA2 follows after a certain delay in the transmit direction (SDA1->C->D->SDA2).
    • When SDA2 turns low it also causes the output of buffer B (= SDA1) to turn low but at a higher 0.75 V level (because of the diode in series with the switch per fig 25).
    • This level (on SDA1) cannot be observed immediately as it is overwritten by the lower low-level of the master.
    • However, when the master releases SDA1, the voltage potential increases and first must pass the upper input threshold of the comparator, VIHT1, to release SDA2. (so SDA2 stays low until this time)
    • SDA1 then increases further until it reaches the buffered output level of VOL1 = 0.75 V, maintained by the receive path.
    • When comparator C turns high, SDA2 is released after the delay in transmit direction. It takes another receive delay until B’s output turns high and fully releases SDA1 to move toward VCC1 potential.

    I hope this helps? If it doesn't, please let us know and we can do a follow-up.

    Best regards,


  • In reply to Abhi Aarey:

    Hi Abhi,

    Yes that helps clear up that confusion. I'll continue to post here as we get more info.

    Thank you!
  • In reply to Cassidy Aarstad:

    Hi Cassidy,

    Like Abhi mentioned, your understanding of ISO1540 functioning is accurate.

    Regarding the issue that customer observed, the power supplies on Side1 and Side2 are independent and neither should affect the other. Please do ask customer to test the same setup with an external pull-up resistor of 4.7kΩ at SDA2 and see if the problem disappears.

    Koteshwar Rao
  • In reply to Koteshwar Rao:

    Hi Abhi and Koteshwar,

    Assuming that the lack of a pull-up on SDA2 is the problem (As is currently suspected) when the FAN is not connected (as stated the SDA2 pull-up is built into the fan), will the device start working correctly once the FAN is connected? Basically, are there any concerns of hot-plugging the FAN onto the bus with this device? Is there any latching issues to be concerned about? While the device may not function correctly without the fan, if it is running incorrectly but then the fan is plugged in, will normal functionality continue

    I think hot-plugging will NOT be an issue and the buses would start functioning normally one clock cycle after the pull-up becomes present. Is this correct?
  • In reply to Cassidy Aarstad:

    Hi Cassidy,

    Your understanding on hot-plugging is accurate Not having a pull-up at SDA2 would lead SDA1 to any state but once the pull-up is connected back, the device should start behaving normal without any issues. We do not foresee any latch-up issues in hot-plugging pull-ups / FAN on SDA2.

    Koteshwar Rao

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