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ISOW7841: Implement stitching capacitance for 6 Layer PCB

Part Number: ISOW7841

Dear Team,

My customer used ISOW7841, but it cannot pass EMI testing.

So they would like to follow the app note slla368a to implement stitching capacitance between GND and VCC.

Their PCB has 6 layer, and the space between each layer is fixed. The PCB design as below:

Layer 1    -------------------- (TOP)

                    d=0.06 mm

Layer 2    --------------------

                    d=0.1 mm

Layer 3    --------------------

                    d=1 mm

Layer 4    --------------------

                    d=0.1 mm

Layer 5    --------------------

                    d=0.06 mm

Layer 6    -------------------- (Bottom)

In the app note, its example is 0.66 mm. But due to the customer cannot change their PCB design, so we only can choose 0.1 mm spacing (Layer 2=GND, Layer 3=VCC) or 1 mm spacing (Layer 3=GND, Layer 4=VCC). 1mm spacing will have higher voltage rating but lower capacitance, am I correct? Which one is better?

If I choose 1 mm spacing, then PCB design will have three ground layer as below. 

Layer 1    -------------------- (TOP)

                    d=0.06 mm

Layer 2    -------------------- (GND)

                    d=0.1 mm

Layer 3    -------------------- (GND)

                    d=1 mm

Layer 4    -------------------- (VCC)

                    d=0.1 mm

Layer 5    -------------------- (GND)

                    d=0.06 mm

Layer 6    -------------------- (Bottom)

Is this the best solution? Please help to advise.

  • Hi Jim,

    Thanks for reaching out to us on E2E. I'm contacting the author of that application note to get some more details to answer your questions. In the meantime, I do have a few questions for you that may help us solve this problem faster:

    • What level are you trying to pass? CISPR22? 
    • Can you provide us with your current schematic and layout? 
      • If you would prefer not to share this on the public forum, please let me know and we can either use E2E private messages or I can provide you with my email address.

    Best regards, 

    Dan

  • In reply to Dan Kisling:

    Hi Dan,

    I have sent you the schematic and layout by mail.

    Thank you.
    Jim
  • In reply to Jim CHEN:

    Hi Jim,

    Like we discussed in the email, both the PCB layout approaches mentioned by you are fine as long as sufficient stitching capacitance value is achieved (>50pF) and isolation voltage requirements are met on PCB as well. Thanks.


    Regards,
    Koteshwar Rao

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