I ask your advice on how to properly combine chassis ground & digital ground. My doubts are related to the large number of documents that I studied and examples that I was able to obtain in the reference design library of Altium Designer boards. AN2587 http://ww1.microchip.com/...ppNotes/00002587A.pdf - Figure 7-3 shows the extent of land within a layer of land through a narrow conductor, and also indicates the required clearance between DGND & CGND. But in the examples from Altium and some documents from TI (EMI / RFI shielding - slideplayer.com/.../) a 2kV capacitor (1-4.7nF) and a 1-10MOhm resistor are used. So what is the best way to combine land? How do you think? P.S. My application contains a set of applications such as:- Ethernet with built-in transformer and divided grounds.- RF antennas with a metallized housing.- Other. Also, my device is powered by an external network adapter from the GST series from MeanWell, but at the same time it has a metal case that contacts external metal structures that are grounded. Grounding from the housing comes to the board through the metallized holes, which are connected to the housing of the device.
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In reply to Koteshwar Rao:
Xilinx Spartan 3AN (NB3000XN):
The grounding is made along the contour of the entire board on all layers and has one merging point with the help of two components C87 (2kV 4.7nF) & R111 (10MOhm) with a loop break in the place of the connector.
TI presentation(- Slide 46):
Grounding is made along the contour of the entire board on all layers and has several filter installation points (CX1, CX2, CX3, CX4 - 2kV 100nF) and a single unification point (RX - 1MOhm), the ground loop without breaking.
Microchip AN2587 (- Figure 7-3):
The grounding is performed by a single loop without breaking (is a current loop or antenna possible?), without connection points, with 3.175 mm insulation between signals.
My application in PDF:
I am interested in the correct architecture of the chassis grounding and interface connectors (Ethernet and others), only within my CASE2 device (CASE1 is not my area of responsibility, so we do not consider it in a specific situation).
In reply to Evgeniy Sokolov:
Hi Koteshwar, My application is almost identical to TPS2388EVM https://www.mouser.it/ds/2/405/sluubq7-1144960.pdf. I want to understand in this connection, the TI engineer, chose two capacitors C17, C18 to 2 kV / 2200pF and why he did not set the resistor to 1-10MOhm as another TI engineer wrote about this in his presentation (slideplayer.com/.../3430548 - RX), and what value of the gap for isolating polygons on layer # 2 (Figure 13.) did he choose, and why did he choose this value (standard or something else? (what did he follow) because Microchip refers to IEC61000-4-2 in which it should be 3.175mm, which visually looks wider than what the TI engineer used)?
In reply to Darwin Fernandez:
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