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EMI/RFI Shielding

Evgeniy Sokolov

Replies: 10

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Hello Community,

I ask your advice on how to properly combine chassis ground & digital ground. My doubts are related to the large number of documents that I studied and examples that I was able to obtain in the reference design library of Altium Designer boards. AN2587 http://ww1.microchip.com/...ppNotes/00002587A.pdf - Figure 7-3 shows the extent of land within a layer of land through a narrow conductor, and also indicates the required clearance between DGND & CGND. But in the examples from Altium and some documents from TI (EMI / RFI shielding - slideplayer.com/.../) a 2kV capacitor (1-4.7nF) and a 1-10MOhm resistor are used. So what is the best way to combine land? How do you think?

P.S. My application contains a set of applications such as:
- Ethernet with built-in transformer and divided grounds.
- RF antennas with a metallized housing.
- Other.

Also, my device is powered by an external network adapter from the GST series from MeanWell, but at the same time it has a metal case that contacts external metal structures that are grounded. Grounding from the housing comes to the board through the metallized holes, which are connected to the housing of the device.

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Koteshwar Rao
- Feb 10, 2019 9:25 AM
Hi Evgeniy,

Thank you for using E2E forum.
One of my colleagues has notified the author of the EMI/RFI shielding presentation that you have referred in your post to look into your query. Meanwhile, it would also be helpful if you could share more details about your applications and relevant block diagrams. Thanks.

Regards,
Koteshwar Rao
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Evgeniy Sokolov
- Feb 10, 2019 12:34 PM
In reply to Koteshwar Rao:

Examples:

Xilinx Spartan 3AN (NB3000XN):

The grounding is made along the contour of the entire board on all layers and has one merging point with the help of two components C87 (2kV 4.7nF) & R111 (10MOhm) with a loop break in the place of the connector.

TI presentation(- Slide 46):

Grounding is made along the contour of the entire board on all layers and has several filter installation points (CX1, CX2, CX3, CX4 - 2kV 100nF) and a single unification point (RX - 1MOhm), the ground loop without breaking.

Microchip AN2587 (- Figure 7-3):

The grounding is performed by a single loop without breaking (is a current loop or antenna possible?), without connection points, with 3.175 mm insulation between signals.

My application in PDF:

3835.block.pdf

I am interested in the correct architecture of the chassis grounding and interface connectors (Ethernet and others), only within my CASE2 device (CASE1 is not my area of responsibility, so we do not consider it in a specific situation).
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Koteshwar Rao
- Feb 11, 2019 2:31 PM
In reply to Evgeniy Sokolov:

Hi Evgeniy,

Thank you for sharing additional information.
I am not an expert on this topic but I think the answer to your question depends a lot on the EMI requirements that the product needs to comply. We typically comment or make suggestion on PCB layout in reference to a specific device like a digital isolator, ADC, amplifier, etc. To comment on the chassis GND architecture to be chosen for an application, I think an expertise on the end application is necessary which I do not posses. Hence, somebody with an expertise in end product design should be able to better answer your question.

I am sorry that I do not have an answer for your question, I can help direct this question to a right person if your question is tied to a particular TI device. Thanks.

Regards,
Koteshwar Rao
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Evgeniy Sokolov
- Feb 12, 2019 6:08 AM
In reply to Koteshwar Rao:

Hi Koteshwar,

My application is almost identical to TPS2388EVM https://www.mouser.it/ds/2/405/sluubq7-1144960.pdf. I want to understand in this connection, the TI engineer, chose two capacitors C17, C18 to 2 kV / 2200pF and why he did not set the resistor to 1-10MOhm as another TI engineer wrote about this in his presentation (slideplayer.com/.../3430548 - RX), and what value of the gap for isolating polygons on layer # 2 (Figure 13.) did he choose, and why did he choose this value (standard or something else? (what did he follow) because Microchip refers to IEC61000-4-2 in which it should be 3.175mm, which visually looks wider than what the TI engineer used)?
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Koteshwar Rao
- Feb 12, 2019 10:30 AM
In reply to Evgeniy Sokolov:

Hi Evgeniy,

Thanks for elaborating on your question and also for mentioning the device your question is closely related to.
I believe the suggestions made in presentation (slideplayer.com/.../3430548) are in relation to weighing scale end product while implementation done on TPS2388EVM is in optimized for PoE product.

I will notify the two authors / product representatives to help you with their comments regarding the components chosen.

In addition, I would like to share you an App Note that talks about EMI/RFI board design (link below) which might help you with some of your questions in relation to EMI/RFI. Thank you.

www.ti.com/lit/an/snla016b/snla016b.pdf

Regards,
Koteshwar Rao
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Evgeniy Sokolov
- Feb 12, 2019 10:58 AM
In reply to Koteshwar Rao:

Hi Koteshwar,
Thanks for the information provided, I will definitely examine the document you submitted. Also I am waiting for an explanation on the choice of certain solutions from the authors of the TPS2388EVM board and the presentation.
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Darwin Fernandez
- Feb 12, 2019 4:50 PM
In reply to Evgeniy Sokolov:

Hi Evgeniy,

C17 and C18 is an extra common mode path for ESD/surge. From an ESD prospective, the energy/surge will find the lowest path impedance. In most cases it is the Earth ground (chassis) connection when it is available on the PSE design itself. However, in some cases like in a midspan application with a plastic encasing and no earthed enclosure, the earth ground connection can be made on the high voltage input of the PSE (50V GND). In some adapters, the output ground of the adapter will connect to the earth ground. So in this case, the C17/18 will allow a path to earth ground via "GND" on the TPS2388EVM schematic.

So C17 and C18 are not absolutely needed and we've seen it removed in designs where a known earth connection will be made.

Note I have yet to see a 1M+ resistor connected similar to high voltage caps to earth on the PSE side of PoE. I have seen it multiple times on PoE PD designs to help as a controlled discharge from residual charge on the chasis to earth ground during ESD/surge. However, majority of designs I have seen do not include this (or it is a non-populated component and used if necessary during testing).

Regards,
Darwin
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Evgeniy Sokolov
- Feb 12, 2019 5:12 PM
In reply to Darwin Fernandez:

Hi Darwin,
Thanks for the detailed answer, you almost confirmed my assumptions. I ask you to give advice on how you would do if you were not sure about the ground (either it is or not - both cases are possible in my situation), but at the same time they would have a metal case for your device Do you install capacitors like C17 & C18 for extra common mode pathing for ESD/surge? And please explain in connection with what you chose the width of the gap between the polygons on Layer # 2 (Figure 13.) on the TPS2388EVM schematic and what is its value in millimeters?
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Darwin Fernandez
- Feb 12, 2019 5:56 PM
In reply to Evgeniy Sokolov:

Hi Evgeniy,

If unsure like in the case for an EVM where a designer can evaluate different ways, I would do both connections and populated/unpopulated as necessary. The energy will go through either of the two paths depending on how its connected at a system level.

If there is metal case and it is connected to earth ground, then majority of the surge will go through there. In our surge tests, we know we will connect the chassis connection to the earth system so we don't have C17/C18 connections.

The spacing between the earth plane and any other plane will depend on the high voltage requirement (1kV high voltage will have wider spacing than 2kV). A designer will usually have their spacing rules/regulations dictated by the safety engineer or that companies requirements. The TPS2388 EVM has a 50 mil (1.27mm) spacing between the two planes. In general, I follow a 20V/mil spacing minimum on my PoE PD EVMs.
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Evgeniy Sokolov
- Feb 12, 2019 6:23 PM
In reply to Darwin Fernandez:

Hi Darwin,
You answered my question as completely as possible. Thank you for the formula for calculating the insulation gap.
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